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1. 发明授权

US06615398B2 Method for dividing ROM and DDFS using the same method 有权
公开(公告)号：US06615398B2
公开(公告)日：2003-09-02
申请号：US10017315
申请日：2001-12-18
申请人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
发明人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
IPC分类号： G06F1750
CPC分类号： G06F1/0356 , G06F1/0328 , G06F2101/04 , G11C17/00
摘要： The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

2. 发明授权

US07027047B2 3D graphics rendering engine for processing an invisible fragment and a method therefor 有权
标题翻译：用于处理不可见片段的3D图形渲染引擎及其方法
公开(公告)号：US07027047B2
公开(公告)日：2006-04-11
申请号：US10730226
申请日：2003-12-08
申请人： Lee-Sup Kim , Chang-Hyo Yu
发明人： Lee-Sup Kim , Chang-Hyo Yu
IPC分类号： G06T17/00
CPC分类号： G06T15/40
摘要： Provided are a 3D graphics rendering engine for processing fragments and a 3D graphics rendering engine method. The 3D graphics rendering engine positions a depth filter having a specific z value in a depth filtering circuit and compares a depth value of each of a plurality of fragments forming a first object being rasterized in a 3D space with a depth value of the depth filter. Then, the 3D graphics rendering engine stores data, which is mapped to the depth filter and corresponds to each of the fragments of the first object, in a storage device, based on the result of the comparison concerning the first object and rasterizes each of a plurality of fragments forming a second object. After that, the 3D graphics rendering engine renders the fragments of the first object and compares a depth value of each of the fragments of the second object in the 3D space with the depth value of the depth filter and removes at least one fragment from the second object that is overlapped with the first object, based on the result of the comparison concerning the second object and based on the data corresponding to each of the fragments of the first object, the data being stored in the storage device. In addition, the 3D graphics rendering engine corrects the position of the depth filter in real time according to the spatial distribution of rendered fragments.
摘要翻译：提供了一种用于处理片段和3D图形渲染引擎方法的3D图形渲染引擎。 3D图形渲染引擎将具有特定z值的深度滤波器定位在深度滤波电路中，并将形成3D空间中被光栅化的第一对象的多个片段中的每一个的深度值与深度滤波器的深度值进行比较。然后，3D图形呈现引擎基于与第一对象的比较结果，将存储在存储装置中的与第一对象的每个片段相对应的深度过滤器并对应的数据存储多个片段形成第二个物体。之后，3D图形呈现引擎呈现第一对象的片段，并将3D空间中第二个对象的每个片段的深度值与深度过滤器的深度值进行比较，并从第二个对象中删除至少一个片段基于与第二对象相关的比较结果，并且基于与第一对象的每个片段对应的数据，存储在存储装置中的数据，与第一对象重叠的对象。此外，3D图形渲染引擎根据渲染片段的空间分布实时校正深度滤镜的位置。

3. 发明授权

US5598361A Discrete cosine transform processor 失效
标题翻译：离散余弦变换处理器
公开(公告)号：US5598361A
公开(公告)日：1997-01-28
申请号：US329382
申请日：1994-10-26
申请人： Tetsu Nagamatsu , Lee-Sup Kim
发明人： Tetsu Nagamatsu , Lee-Sup Kim
IPC分类号： G06F17/14
CPC分类号： G06F17/147
摘要： A discrete cosine transform processor for executing discrete cosine transform calculations in both forward and inverse directions on the basis of previously stored product addition data has a memory having a first memory section for storing product addition calculation data for the forward direction transformation and a second memory section for storing product addition calculation data for the inverse direction transformation other than data in common to those stored in the first memory section; and sign inverter for inverting signs of the data used in common for the inverse direction transformation, among the data stored in the first memory section. The memory preferably includes first memory for storing product addition data corresponding to even-order coefficients and second memory for storing product addition data corresponding to odd-order coefficients; and only the second memory stores data used in common for both the forward and inverse direction transformations in the first memory thereof.
摘要翻译：用于基于先前存储的乘积相加数据在前向和反向方向上执行离散余弦变换计算的离散余弦变换处理器具有存储器，其具有用于存储正向变换的乘积加法运算数据的第一存储器部分和第二存储器部分用于将除了与存储在第一存储器部分中的数据相同的数据以外的逆向变换的乘积计算数据存储; 并且在存储在第一存储器部分中的数据中，用于反转用于反转用于逆向变换的共同使用的数据的符号的反相器。存储器优选地包括用于存储对应于偶数系数的乘积加法数据的第一存储器和用于存储对应于奇数系数的乘积加法数据的第二存储器; 并且只有第二存储器存储在其第一存储器中正向和反向转换两者共同使用的数据。

4. 发明授权

US09092906B2 Graphic processor and method of early testing visibility of pixels 有权
标题翻译：图形处理器和早期测试像素可见性的方法
公开(公告)号：US09092906B2
公开(公告)日：2015-07-28
申请号：US13277665
申请日：2011-10-20
申请人： Chang-Hyo Yu , Lee-Sup Kim , Hong-Yun Kim
发明人： Chang-Hyo Yu , Lee-Sup Kim , Hong-Yun Kim
IPC分类号： G06T15/40 , G06T15/00 , G09G5/39
CPC分类号： G06T15/40 , G06T7/194 , G06T11/40 , G06T15/00 , G06T15/005 , G06T15/405 , G09G5/39
摘要： A graphic processor includes a rasterizer configured to process vertex data to generate fragment data based on a maximum depth value, a minimum depth value, and a mask bit of each pixel included in one tile, each mask bit indicating whether each pixel is drawn or not, the vertex data including three dimensional information of the pixels, a pixel shader configured to process the fragment data to generate color data, and a raster operation unit configured to convert the color data to pixel data to be displayed.
摘要翻译：图形处理器包括被配置为基于最大深度值，最小深度值和包括在一个图块中的每个像素的屏蔽位来处理顶点数据以生成片段数据的光栅化器，每个掩码位指示每个像素是否被绘制，包括像素的三维信息的顶点数据，被配置为处理片段数据以生成颜色数据的像素着色器，以及被配置为将颜色数据转换为要显示的像素数据的光栅操作单元。

5. 发明申请

US20120212488A1 GRAPHIC PROCESSOR AND METHOD OF EARLY TESTING VISIBILITY OF PIXELS 有权
标题翻译：图形处理器和早期测试像素可见性的方法
公开(公告)号：US20120212488A1
公开(公告)日：2012-08-23
申请号：US13277665
申请日：2011-10-20
申请人： Chang-Hyo YU , Lee-Sup Kim , Hong-Yun Kim
发明人： Chang-Hyo YU , Lee-Sup Kim , Hong-Yun Kim
IPC分类号： G06T15/40
CPC分类号： G06T15/40 , G06T7/194 , G06T11/40 , G06T15/00 , G06T15/005 , G06T15/405 , G09G5/39
摘要： A graphic processor includes a rasterizer configured to process vertex data to generate fragment data based on a maximum depth value, a minimum depth value, and a mask bit of each pixel included in one tile, each mask bit indicating whether each pixel is drawn or not, the vertex data including three dimensional information of the pixels, a pixel shader configured to process the fragment data to generate color data, and a raster operation unit configured to convert the color data to pixel data to be displayed.
摘要翻译：图形处理器包括被配置为基于最大深度值，最小深度值和包括在一个图块中的每个像素的屏蔽位来处理顶点数据以生成片段数据的光栅化器，每个掩码位指示每个像素是否被绘制，包括像素的三维信息的顶点数据，被配置为处理片段数据以生成颜色数据的像素着色器，以及被配置为将颜色数据转换为要显示的像素数据的光栅操作单元。

6. 发明授权

US5673214A Discrete cosine transform processor 失效
标题翻译：离散余弦变换处理器
公开(公告)号：US5673214A
公开(公告)日：1997-09-30
申请号：US704922
申请日：1996-08-28
申请人： Lee-Sup Kim , Tetsu Nagamatsu , Takayasu Sakurai
发明人： Lee-Sup Kim , Tetsu Nagamatsu , Takayasu Sakurai
IPC分类号： H04N19/60 , G06F17/14 , G06T1/20 , G06T9/00 , H04N1/41 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/625
CPC分类号： G06F17/147 , G06T9/007
摘要： Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image data to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.
摘要翻译：公开了一种改进的离散余弦变换处理器，包括用于接收要处理的图像数据的输入单元，用于预先存储关于图像输入数据和变换矩阵分量预先实现的乘法和累加计算的结果的存储单元，使得相同值从相同的读取行读取; 用于选择读取行的解码单元，其中由多个位组成的图像输入数据的每个位值用作一段地址数据; 用于累积从存储单元读取的数据的积累单元和用于输出积累处理结果作为输出数据的输出单元。存储单元在进行乘法运算和累计运算时，共同使用共同的数据，因此能够减小存储容量，从而可以减少芯片面积。

7. 发明授权

US07619456B2 Wide frequency multi-phase signal generator with variable duty ratio and method thereof 有权
标题翻译：具有可变占空比的宽频多相信号发生器及其方法
公开(公告)号：US07619456B2
公开(公告)日：2009-11-17
申请号：US11826511
申请日：2007-07-16
申请人： Byung-Guk Kim , Lee-Sup Kim , Kwang-Il Park
发明人： Byung-Guk Kim , Lee-Sup Kim , Kwang-Il Park
IPC分类号： H03H11/16 , H03K5/13 , H03K3/00
CPC分类号： H03K5/15013
摘要： A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.
摘要翻译：多相信号发生器可以包括配置成接收第一差分输入信号和第二差分输入信号的占空比控制缓冲器，并且基于控制电压产生具有可变占空比的第一差分输出信号和第二差分输出信号，第一边缘组合器，被配置为基于相应的第一和第二差分输出信号的第一边缘产生第一脉冲信号;第二边缘组合器，被配置为基于相应的第一和第二差分输出信号的第二边缘产生第二脉冲信号，以及控制电压发生器，被配置为响应于通过对所述第一和第二脉冲信号执行逻辑运算而获得的逻辑信号来产生所述控制电压。

8. 发明申请

US20080025451A1 Multi-phase signal generator and method thereof 有权
标题翻译：多相信号发生器及其方法
公开(公告)号：US20080025451A1
公开(公告)日：2008-01-31
申请号：US11826511
申请日：2007-07-16
申请人： Byung-Guk Kim , Lee-Sup Kim , Kwang-Il Park
发明人： Byung-Guk Kim , Lee-Sup Kim , Kwang-Il Park
IPC分类号： H04L7/06
CPC分类号： H03K5/15013
摘要： A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.
摘要翻译：多相信号发生器可以包括配置成接收第一差分输入信号和第二差分输入信号的占空比控制缓冲器，并且基于控制电压产生具有可变占空比的第一差分输出信号和第二差分输出信号，第一边缘组合器，被配置为基于相应的第一和第二差分输出信号的第一边缘产生第一脉冲信号;第二边缘组合器，被配置为基于相应的第一和第二差分输出信号的第二边缘产生第二脉冲信号，以及控制电压发生器，被配置为响应于通过对所述第一和第二脉冲信号执行逻辑运算而获得的逻辑信号来产生所述控制电压。

9. 发明申请

US20050068319A1 3D graphics rendering engine for processing an invisible fragment and a method therefor 有权
标题翻译：用于处理不可见片段的3D图形渲染引擎及其方法
公开(公告)号：US20050068319A1
公开(公告)日：2005-03-31
申请号：US10730226
申请日：2003-12-08
申请人： Lee-Sup Kim , Chang-Hyo Yu
发明人： Lee-Sup Kim , Chang-Hyo Yu
IPC分类号： G06T15/10 , G06T15/00 , G06T15/40
CPC分类号： G06T15/40
摘要： Provided are a 3D graphics rendering engine for processing fragments and a 3D graphics rendering engine method. The 3D graphics rendering engine positions a depth filter having a specific z value in a depth filtering circuit and compares a depth value of each of a plurality of fragments forming a first object being rasterized in a 3D space with a depth value of the depth filter. Then, the 3D graphics rendering engine stores data, which is mapped to the depth filter and corresponds to each of the fragments of the first object, in a storage device, based on the result of the comparison concerning the first object and rasterizes each of a plurality of fragments forming a second object. After that, the 3D graphics rendering engine renders the fragments of the first object and compares a depth value of each of the fragments of the second object in the 3D space with the depth value of the depth filter and removes at least one fragment from the second object that is overlapped with the first object, based on the result of the comparison concerning the second object and based on the data corresponding to each of the fragments of the first object, the data being stored in the storage device. In addition, the 3D graphics rendering engine corrects the position of the depth filter in real time according to the spatial distribution of rendered fragments.
摘要翻译：提供了一种用于处理片段和3D图形渲染引擎方法的3D图形渲染引擎。 3D图形渲染引擎将具有特定z值的深度滤波器定位在深度滤波电路中，并将形成3D空间中被光栅化的第一对象的多个片段中的每一个的深度值与深度滤波器的深度值进行比较。然后，3D图形呈现引擎基于与第一对象的比较结果，将存储在存储装置中的与第一对象的每个片段相对应的深度过滤器并对应的数据存储多个片段形成第二个物体。之后，3D图形呈现引擎呈现第一对象的片段，并将3D空间中第二个对象的每个片段的深度值与深度过滤器的深度值进行比较，并从第二个对象中删除至少一个片段基于与第二对象相关的比较结果，并且基于与第一对象的每个片段对应的数据，存储在存储装置中的数据，与第一对象重叠的对象。此外，3D图形渲染引擎根据渲染片段的空间分布实时校正深度滤镜的位置。

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