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1. 发明授权

US08755215B2 Resistive memory device 有权
标题翻译：电阻式存储器件
公开(公告)号：US08755215B2
公开(公告)日：2014-06-17
申请号：US13563290
申请日：2012-07-31
申请人： Hyunsu Yoon , Youncheul Kim
发明人： Hyunsu Yoon , Youncheul Kim
IPC分类号： G11C13/00 , G11C29/26 , G11C29/00
CPC分类号： G11C13/0002 , G06F11/1048 , G11C17/16 , G11C17/18 , G11C29/26 , G11C29/785 , G11C2029/0411 , G11C2213/70
摘要： A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the first cell array, and a second error correction cell array configured to share column lines of the first error correction cell array.
摘要翻译：电阻性存储器件包括被配置为存储数据的第一单元阵列，被配置为共享第一单元阵列的列线的第二单元阵列，配置为存储对应于要存储的数据的纠错码的第一纠错单元阵列以及配置成共享第一纠错单元阵列的列线的第二纠错单元阵列。

2. 发明授权

US08918683B2 One-time program cell array circuit and memory device including the same 有权
标题翻译：一次性编程单元阵列电路和包含其的存储器件
公开(公告)号：US08918683B2
公开(公告)日：2014-12-23
申请号：US13619115
申请日：2012-09-14
申请人： Hyunsu Yoon , Youncheul Kim , Kwanweon Kim , Jeongtae Hwang
发明人： Hyunsu Yoon , Youncheul Kim , Kwanweon Kim , Jeongtae Hwang
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.
摘要翻译：一次性编程单元阵列电路包括被配置为包括多个一次性程序存储单元的单元阵列，并且编程输入的程序数据并输出存储的程序数据作为读取数据，代码生成电路被配置为生成在编程操作期间基于输入的程序数据在单元阵列中编程的纠错码; 以及错误检测电路，被配置为基于在读取操作期间从单元阵列输出的误差校正码和读取数据来检测读取的数据的错误，并响应于第一使能信号而被使能或禁用。可以通过在增加可靠性的同时控制纠错方案的启用或禁用来解决通过将错误校正方案应用于一次性程序单元阵列电路所引起的问题。

3. 发明申请

US20140036569A1 RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件
公开(公告)号：US20140036569A1
公开(公告)日：2014-02-06
申请号：US13563290
申请日：2012-07-31
申请人： Hyunsu YOON , Youncheul Kim
发明人： Hyunsu YOON , Youncheul Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G06F11/1048 , G11C17/16 , G11C17/18 , G11C29/26 , G11C29/785 , G11C2029/0411 , G11C2213/70
摘要： A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the first cell array, and a second error correction cell array configured to share column lines of the first error correction cell array.
摘要翻译：电阻性存储器件包括被配置为存储数据的第一单元阵列，被配置为共享第一单元阵列的列线的第二单元阵列，配置为存储对应于要存储的数据的纠错码的第一纠错单元阵列以及配置成共享第一纠错单元阵列的列线的第二纠错单元阵列。

4. 发明申请

US20140082438A1 ONE-TIME PROGRAM CELL ARRAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：一次性程序单元阵列电路和包括其的存储器件
公开(公告)号：US20140082438A1
公开(公告)日：2014-03-20
申请号：US13619115
申请日：2012-09-14
申请人： Hyunsu YOON , Youncheul Kim , Kwanweon Kim , Jeongtae Hwang
发明人： Hyunsu YOON , Youncheul Kim , Kwanweon Kim , Jeongtae Hwang
IPC分类号： H03M13/29 , G06F11/20
CPC分类号： G06F11/1008
摘要： A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.
摘要翻译：一次性编程单元阵列电路包括被配置为包括多个一次性程序存储单元的单元阵列，并且编程输入的程序数据并输出存储的程序数据作为读取数据，代码生成电路被配置为生成在编程操作期间基于输入的程序数据在单元阵列中编程的纠错码; 以及错误检测电路，被配置为基于在读取操作期间从单元阵列输出的误差校正码和读取数据来检测读取的数据的错误，并响应于第一使能信号而被使能或禁用。可以通过在增加可靠性的同时控制纠错方案的启用或禁用来解决通过将错误校正方案应用于一次性程序单元阵列电路所引起的问题。

5. 发明授权

US09007802B2 E-fuse array circuit 有权
标题翻译：电熔丝阵列电路
公开(公告)号：US09007802B2
公开(公告)日：2015-04-14
申请号：US13610451
申请日：2012-09-11
申请人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
发明人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
IPC分类号： G11C17/18 , G11C17/04 , G11C17/16
CPC分类号： G11C17/18 , G11C17/04 , G11C17/16
摘要： An e-fuse array circuit includes a program gate line and a word line gate line that are stretched in parallel to each other, and a metal line formed over the program gate line and the word line gate line to cover the program gate line and the word line gate line, the metal line connected to the program gate line through a plurality of contact plugs disposed at a given distance.
摘要翻译：电子熔丝阵列电路包括彼此平行拉伸的编程栅极线和字线栅极线，以及形成在编程栅极线和字线栅极线上的金属线，以覆盖编程栅极线和字线栅极线，金属线通过设置在给定距离处的多个接触插塞连接到编程门线。

6. 发明授权

US09015463B2 Memory device, memory system including a non-volatile memory configured to output a repair data in response to an initialization signal 有权
标题翻译：存储器装置，包括被配置为响应于初始化信号输出修复数据的非易失性存储器的存储器系统
公开(公告)号：US09015463B2
公开(公告)日：2015-04-21
申请号：US13601629
申请日：2012-08-31
申请人： Jeongsu Jeong , Youncheul Kim , Gwangyoung Stanley Jeong , Bokmoon Kang
发明人： Jeongsu Jeong , Youncheul Kim , Gwangyoung Stanley Jeong , Bokmoon Kang
IPC分类号： G06F15/177 , G06F11/00 , G11C16/20 , G11C29/00 , G11C7/20 , G11C29/44
CPC分类号： G11C16/20 , G11C7/20 , G11C29/82 , G11C2029/4402
摘要： A memory device includes a non-volatile memory configured to store a repair data and output the repair data in response to an initialization signal, a plurality of registers configured to store the repair data outputted from the non-volatile memory, a plurality of memory banks configured to replace normal cells with redundant cells by using the repair data stored in corresponding registers among the plurality of registers, a verification circuit configured to generate a completion signal for informing that transfer of the repair data from the non-volatile memory to the plurality of registers is completed, and an output circuit configured to output the completion signal to a device other than the memory device.
摘要翻译：存储器装置包括：非易失性存储器，被配置为存储修复数据并响应于初始化信号输出修复数据;多个寄存器，被配置为存储从非易失性存储器输出的修复数据;多个存储体配置为通过使用存储在所述多个寄存器中的相应寄存器中的修复数据来替换正常单元，所述验证电路被配置为生成用于通知所述修复数据从所述非易失性存储器到所述多个寄存器的传送的完成信号寄存器完成，并且输出电路被配置为将完成信号输出到除存储器件之外的器件。

7. 发明申请

US20140071779A1 E-FUSE ARRAY CIRCUIT 有权
标题翻译：电子保险丝阵列电路
公开(公告)号：US20140071779A1
公开(公告)日：2014-03-13
申请号：US13610451
申请日：2012-09-11
申请人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
发明人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/04 , G11C17/16
摘要： An e-fuse array circuit includes a program gate line and a word line gate line that are stretched in parallel to each other, and a metal line formed over the program gate line and the word line gate line to cover the program gate line and the word line gate line, the metal line connected to the program gate line through a plurality of contact plugs disposed at a given distance.
摘要翻译：电子熔丝阵列电路包括彼此平行拉伸的编程栅极线和字线栅极线，以及形成在编程栅极线和字线栅极线上的金属线，以覆盖编程栅极线和字线栅极线，金属线通过设置在给定距离处的多个接触插塞连接到编程门线。

8. 发明申请

US20140068241A1 MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD FOR OPERATING THE MEMORY SYSTEM 有权
标题翻译：存储器件，包括其的存储器系统以及用于操作存储器系统的方法
公开(公告)号：US20140068241A1
公开(公告)日：2014-03-06
申请号：US13601629
申请日：2012-08-31
申请人： Jeongsu JEONG , Youncheul Kim , Gwangyoung Stanley Jeong , Bokmoon Kang
发明人： Jeongsu JEONG , Youncheul Kim , Gwangyoung Stanley Jeong , Bokmoon Kang
IPC分类号： G06F15/177 , G06F13/00 , G11C7/00
CPC分类号： G11C16/20 , G11C7/20 , G11C29/82 , G11C2029/4402
摘要： A memory device includes a non-volatile memory configured to store a repair data and output the repair data in response to an initialization signal, a plurality of registers configured to store the repair data outputted from the non-volatile memory, a plurality of memory banks configured to replace normal cells with redundant cells by using the repair data stored in corresponding registers among the plurality of registers, a verification circuit configured to generate a completion signal for informing that transfer of the repair data from the non-volatile memory to the plurality of registers is completed, and an output circuit configured to output the completion signal to a device other than the memory device.
摘要翻译：存储器装置包括：非易失性存储器，被配置为存储修复数据并响应于初始化信号输出修复数据;多个寄存器，被配置为存储从非易失性存储器输出的修复数据;多个存储体配置为通过使用存储在所述多个寄存器中的相应寄存器中的修复数据来替换正常单元，所述验证电路被配置为生成用于通知所述修复数据从所述非易失性存储器到所述多个寄存器的传送的完成信号寄存器完成，并且输出电路被配置为将完成信号输出到除存储器件之外的器件。

9. 发明授权

US08780612B2 Resistive memory device and programming method thereof 有权
标题翻译：电阻式存储器件及其编程方法
公开(公告)号：US08780612B2
公开(公告)日：2014-07-15
申请号：US13591812
申请日：2012-08-22
申请人： Youncheul Kim , Jeongsu Jeong , Yonggu Kang
发明人： Youncheul Kim , Jeongsu Jeong , Yonggu Kang
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0064
摘要： A method for programming a resistive memory device includes: programming a resistive memory; generating a verification data based on comparison result of a voltage, which is generated from a current flowing through the resistive memory, and a verification reference voltage which is higher than a read reference voltage used for a normal read operation; and deciding whether to end a program operation based on the verification data.
摘要翻译：一种用于编程电阻式存储器件的方法包括：对电阻性存储器进行编程; 基于从流过电阻性存储器的电流产生的电压的比较结果和高于用于正常读取操作的读取参考电压的验证参考电压产生验证数据; 以及基于验证数据来决定是否结束程序操作。

10. 发明授权

US08767434B2 E-fuse array circuit 有权
标题翻译：电熔丝阵列电路
公开(公告)号：US08767434B2
公开(公告)日：2014-07-01
申请号：US13610802
申请日：2012-09-11
申请人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
发明人： Sungju Son , Youncheul Kim , Sungho Kim , Dongue Ko
IPC分类号： G11C17/16 , G11C17/00 , H01L23/525 , H01L23/62 , G11C29/02 , G11C29/00
CPC分类号： G11C17/18 , G11C17/00 , G11C17/16 , G11C17/165 , G11C29/027 , G11C29/787 , G11C2229/763 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.
摘要翻译：电子熔丝阵列电路包括：垂直栅极类型的电子熔丝晶体管，其被配置为具有用于接收编程栅极线的电压并且在漏极端子和源极端子之间浮置的栅极的栅极; 以及掩埋栅极型选择晶体管，其配置为具有用于接收字线栅极线的电压的栅极，并且利用位线将漏极端子和源极端子之间的另一个电连接/断开。

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