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1. 发明授权

US10852495B2 Microelectronic package communication using radio interfaces connected through wiring 有权
公开(公告)号：US10852495B2
公开(公告)日：2020-12-01
申请号：US15746792
申请日：2015-09-25
申请人： Intel Corporation
发明人： Shawna Liff , Adel A. Elsherbini , Telesphor Kamgaing , Sasha N. Oster , Gaurav Chawla
IPC分类号： G02B6/42 , G06F13/14 , H01P5/00 , H01Q13/10 , H04B1/40 , H04B7/00 , H04M9/06 , G06F13/00
摘要： Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

2. 发明授权

US10205292B2 Socket contact techniques and configurations 有权
公开(公告)号：US10205292B2
公开(公告)日：2019-02-12
申请号：US15716356
申请日：2017-09-26
申请人： INTEL CORPORATION
发明人： Dhanya Athreya , Gaurav Chawla , Kemal Aygun , Glen P. Gordon , Sarah M. Canny , Jeffory L. Smalley , Srikant Nekkanty , Michael Garcia , Joshua D. Heppner
IPC分类号： H01R33/76 , H01L23/32 , H01L23/498
摘要： Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

3. 发明授权

US09615483B2 Techniques and configurations associated with a package load assembly 有权
公开(公告)号：US09615483B2
公开(公告)日：2017-04-04
申请号：US14484896
申请日：2014-09-12
申请人： Intel Corporation
发明人： Gaurav Chawla , Joshua D. Heppner , Vijaykumar Krithivasan , Michael Garcia , Kuang C. Liu , Rajasekaran Swaminathan
IPC分类号： H05K7/20 , H01L23/367 , H01L23/40 , H01L23/433
CPC分类号： H05K7/20 , H01L23/3675 , H01L23/4006 , H01L23/433 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

4. 发明授权

US09490560B2 Multi-array bottom-side connector using spring bias 有权
标题翻译：使用弹簧偏置的多阵列底侧连接器
公开(公告)号：US09490560B2
公开(公告)日：2016-11-08
申请号：US14576735
申请日：2014-12-19
申请人： INTEL CORPORATION
发明人： Gaurav Chawla , David J. Llapitan , Jeffory L. Smalley , Tejinder Pal Aulakh , Vijaykumar Krithivasan , Donald T. Tran
IPC分类号： H01R12/79 , H05K7/10 , H01R43/20 , G06F1/18
CPC分类号： H01R12/79 , G06F1/18 , H01R43/205 , H05K7/1069 , H05K7/1092
摘要： A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
摘要翻译：描述了使用弹簧偏压的多阵列底侧阵列的连接器。在一个示例中，连接器包括连接器壳体，连接器壳体具有底表面，以及与底表面相对的多个弹性连接器，以电连接到集成电路封装的对应的多个焊盘;电缆连接器，用于电连接电缆的弹性连接器，具有压靠电路板的底表面的基板和与底表面相对的顶表面，以及联接在基板和连接器底表面之间的多个弹簧构件，用于将基板底部表面靠在系统板上，并将连接器外壳连接件按压在包装上。

5. 发明授权

US09478881B2 Snap connector for socket assembly and associated techniques and configurations 有权
标题翻译：用于插座组件和相关技术和配置的卡口连接器
公开(公告)号：US09478881B2
公开(公告)日：2016-10-25
申请号：US14642078
申请日：2015-03-09
申请人： Intel Corporation
发明人： Zhichao Zhang , Gaurav Chawla , Rajasekaran Swaminathan , Kemal Aygun , Li Sun
IPC分类号： H01R13/193 , H01R12/51 , H01R12/70 , H01R43/20
CPC分类号： H01R12/7076 , H01R43/205 , H05K7/1038
摘要： Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于插座组件和相关技术和配置的卡扣连接器。在一个实施例中，插座组件包括插座主体，该插座主体具有从插座本体的第一侧延伸到插座主体的第二侧的多个开口，以在第一侧和第二侧之间提供电路径，第二侧与所述第一侧相对设置，其中所述多个开口的与所述插座主体的第一侧相邻的开口的保持部分成形为通过由所述插座主体施加的弹力来保持模具组件的对应电接触，当电触点位于保持部分内时的电接触。可以描述和/或要求保护其他实施例。

6. 发明申请

US20150249298A1 CONNECTOR ASSEMBLY AND METHOD 审中-公开
标题翻译：连接器总成和方法
公开(公告)号：US20150249298A1
公开(公告)日：2015-09-03
申请号：US14563641
申请日：2014-12-08
申请人： Intel Corporation
发明人： Gaurav Chawla , Joshua D. Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
IPC分类号： H01R12/72 , H01R12/70 , H01L23/34 , H01R13/11
CPC分类号： H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
摘要： Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
摘要翻译：显示连接器和耦合封装和管芯的方法。所选择的示例包括具有两个或更多台阶的插头和插座，其具有沿着梯田提供的触点。连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。

7. 发明授权

US08915747B2 Connector assembly with integrated pitch translation 有权
标题翻译：具有集成音调翻译的连接器组件
公开(公告)号：US08915747B2
公开(公告)日：2014-12-23
申请号：US13826998
申请日：2013-03-14
申请人： Intel Corporation
发明人： Gaurav Chawla , Rajasekaran Raja Swaminathan , Donald T. Tran
IPC分类号： H01R12/00 , H01R12/71
CPC分类号： H01R12/71 , H01R12/53 , H01R12/57 , H01R25/006
摘要： This disclosure relates generally to a connector assembly. Optionally, first conductive members form a first row. Second conductive members include a first subset forming a second row and a second subset forming a third row, the second and third rows being parallel and offset with respect to one another. Individual ones of the first and second conductive members are arranged to be coupled at a first end to a corresponding contact. At least one of the first and second subsets has a vertical displacement to form a common row of the second conductive members at a second end of the second conductive members. Individual ones of the first conductive members are arranged to be coupled proximate a second end of the first conductive members to the second end of a corresponding one of the second conductive members.
摘要翻译：本公开总体上涉及连接器组件。可选地，第一导电构件形成第一行。第二导电构件包括形成第二行的第一子集和形成第三行的第二子集，第二和第三行相对于彼此平行和偏移。第一和第二导电构件中的各个被布置成在第一端耦合到相应的触点。第一和第二子集中的至少一个具有垂直位移，以在第二导电构件的第二端处形成第二导电构件的公共排。第一导电构件中的各个被布置成在第一导电构件的第二端附近耦合到相应的一个第二导电构件的第二端。

8. 发明授权

US11516915B2 Reduced capacitance land pad 有权
公开(公告)号：US11516915B2
公开(公告)日：2022-11-29
申请号：US16559286
申请日：2019-09-03
申请人： Intel Corporation
发明人： Zhichao Zhang , Tao Wu , Gaurav Chawla , Jeffrey Lee
IPC分类号： H05K1/11 , H05K3/40 , H05K3/46 , H05K3/34 , H05K1/02
摘要： A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

9. 发明授权

US09780510B2 Socket contact techniques and configurations 有权
公开(公告)号：US09780510B2
公开(公告)日：2017-10-03
申请号：US14764931
申请日：2014-09-26
申请人： INTEL CORPORATION
发明人： Dhanya Athreya , Gaurav Chawla , Kemal Aygun , Glen P. Gordon , Sarah M. Canny , Jeffory L. Smalley , Srikant Nekkanty , Michael Garcia , Joshua D. Heppner
IPC分类号： H01R24/00 , H01R33/76 , H01L23/32 , H01L23/498
CPC分类号： H01R33/7685 , H01L23/32 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

10. 发明申请

US20160079150A1 TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY 有权
标题翻译：与包装装配相关的技术和配置
公开(公告)号：US20160079150A1
公开(公告)日：2016-03-17
申请号：US14484896
申请日：2014-09-12
申请人： Intel Corporation
发明人： Gaurav Chawla , Joshua D. Heppner , Vijaykumar Krithivasan , Michael Garcia , Kuang C. Liu , Rajasekaran Swaminathan
IPC分类号： H01L23/498 , H01L23/36 , H01L21/48 , B23P15/26
CPC分类号： H05K7/20 , H01L23/3675 , H01L23/4006 , H01L23/433 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
摘要翻译：本公开的实施例涉及与封装负载组件相关联的技术和配置。在一个实施例中，包装负载组件可以包括框架，该框架被配置为围绕包装衬底的管芯区域形成周边，该封装衬底具有构造成与封装衬底的表面耦合的第一表面和与第一表面相对设置的第二表面。框架可以包括设置在第二表面上的可变形构件，其可以被配置为与散热器的底座相耦合，以经由框架分布施加在散热器和封装衬底之间的力，并且可以在应用力，其可以允许散热器的底部接触在封装衬底的管芯区域内的集成散热器的表面。

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