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1. 发明授权

US11150905B2 Efficiency for coordinated start interpretive execution exit for a multithreaded processor 有权
公开(公告)号：US11150905B2
公开(公告)日：2021-10-19
申请号：US15717487
申请日：2017-09-27
申请人： International Business Machines Corporation
发明人： Jonathan D. Bradbury , Fadi Y. Busaba , Mark S. Farrell , Charles W. Gainey, Jr. , Dan F. Greiner , Lisa C. Heller , Jeffrey P. Kubala , Damian L. Osisek , Donald W. Schmidt , Timothy J. Siegel
IPC分类号： G06F9/30 , G06F9/455 , G06F9/52
摘要： A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

2. 发明授权

US10776112B2 Performing an operation absent host intervention 有权
公开(公告)号：US10776112B2
公开(公告)日：2020-09-15
申请号：US16441582
申请日：2019-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles W. Gainey, Jr. , Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Gustav E. Sittmann, III
IPC分类号： G06F13/00 , G06F9/30 , G06F9/455 , G06F12/0891 , G06F12/02 , G06F12/1009 , G06F3/06 , G06F12/08 , G06F12/12
摘要： Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

3. 发明授权

US10423539B2 Dynamic address translation with access control in an emulator environment 有权
公开(公告)号：US10423539B2
公开(公告)日：2019-09-24
申请号：US15830160
申请日：2017-12-04
申请人： International Business Machines Corporation
发明人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F12/00 , G06F12/1027 , G06F12/1009 , G06F12/14 , G06F12/02 , G06F12/1036 , G06F9/30 , G06F13/00 , G06F13/28
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

4. 发明申请

US20180365165A1 SUSPENDING TRANSLATION LOOK-ASIDE BUFFER PURGE EXECUTION IN A MULTI-PROCESSOR ENVIRONMENT 审中-公开
公开(公告)号：US20180365165A1
公开(公告)日：2018-12-20
申请号：US15856140
申请日：2017-12-28
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Ute Gaertner , Lisa C. Heller , Markus Helms , Thomas Köhler , Frank Lehnert , Jennifer A. Navarro , Rebecca S. Wisniewski
IPC分类号： G06F12/1027 , G06F12/1009
摘要： Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

5. 发明授权

US09898289B2 Coordinated start interpretive execution exit for a multithreaded processor 有权
公开(公告)号：US09898289B2
公开(公告)日：2018-02-20
申请号：US14518095
申请日：2014-10-20
申请人： International Business Machines Corporation
发明人： Jonathan D. Bradbury , Fadi Y. Busaba , Mark S. Farrell , Charles W. Gainey, Jr. , Dan F. Greiner , Lisa C. Heller , Jeffrey P. Kubala , Damian L. Osisek , Donald W. Schmidt , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/46 , G06F9/48 , G06F9/455 , G06F9/52
CPC分类号： G06F9/30065 , G06F9/30145 , G06F9/45533 , G06F9/466 , G06F9/4881 , G06F9/52 , G06F9/522
摘要： A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

6. 发明授权

US09606799B2 Performing a clear operation absent host intervention 有权
公开(公告)号：US09606799B2
公开(公告)日：2017-03-28
申请号：US15166886
申请日：2016-05-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Charles W. Gainey, Jr. , Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Gustav E. Sittmann, III
IPC分类号： G06F12/00 , G06F13/00 , G06F9/30 , G06F9/455 , G06F12/0891 , G06F12/02 , G06F12/1009 , G06F3/06 , G06F12/08
CPC分类号： G06F9/30043 , G06F3/0604 , G06F3/0605 , G06F3/0644 , G06F3/0652 , G06F3/0664 , G06F3/0673 , G06F9/30003 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/45537 , G06F9/45545 , G06F9/45558 , G06F12/023 , G06F12/08 , G06F12/0891 , G06F12/1009 , G06F2009/45583 , G06F2212/1041 , G06F2212/151 , G06F2212/656 , G06F2212/657 , G06F2212/69
摘要： Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

7. 发明授权

US09372805B2 Operating on translation look-aside buffers in a multiprocessor environment 有权
标题翻译：在多处理器环境中操作翻译后备缓冲区
公开(公告)号：US09372805B2
公开(公告)日：2016-06-21
申请号：US14034848
申请日：2013-09-24
申请人： International Business Machines Corporation
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46 , G06F12/10 , G06F9/52
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.
摘要翻译：一个方面包括在包括多个逻辑分区作为区域的多处理器环境中对翻译后备缓冲器（TLB）进行操作的方法。该方法包括同时从第一区域的第一处理器接收第一静默请求，以使包括第一区域的第一组区域的处理器静止，并从第二区域的第二处理器接收第二静默请求，以使第二区域的处理器静止一组区域包括第二个区域。第二组区域由与第一组区域分开的区域组成。基于接收到第一个静默请求，只有第一组区域的处理器停顿。基于处于静止状态的第一组区域的处理器，对TLB执行第一操作。基于正在执行的第一操作，第一组区域的处理器是不静默的。

8. 发明申请

US20160140002A1 RECOVERY IMPROVEMENT FOR QUIESCED SYSTEMS 有权
公开(公告)号：US20160140002A1
公开(公告)日：2016-05-19
申请号：US14571512
申请日：2014-12-16
申请人： International Business Machines Corporation
发明人： Michael Fee , Ute Gaertner , Lisa C. Heller , Frank Lehnert , Jennifer A. Navarro , Rebecca S. Wisniewski
IPC分类号： G06F11/20 , G06F12/08 , G06F11/10
CPC分类号： G06F11/1064 , G06F11/1044 , G06F11/1402 , G06F11/1484 , G06F11/2028 , G06F11/2041 , G06F12/0811 , G06F12/084 , G06F2201/815 , G06F2212/314
摘要： Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

9. 发明授权

US09092382B2 Reducing microprocessor performance loss due to translation table coherency in a multi-processor system 有权
标题翻译：由于多处理器系统中的转换表一致性，降低了微处理器的性能损失
公开(公告)号：US09092382B2
公开(公告)日：2015-07-28
申请号：US13667687
申请日：2012-11-02
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F13/00 , G06F13/28 , G06F12/16 , G06F13/16 , G06F12/10 , G06F12/08
CPC分类号： G06F12/16 , G06F12/08 , G06F12/0815 , G06F12/1027 , G06F13/1689 , G06F2212/1016 , G06F2212/682 , G06F2212/683
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元提取要在多处理器系统中执行的第一条指令。 TCUEP将第一个指令时间戳与每个第一个指令相关联。 TCUEP接收到多处理器一致性操作，并且在接收到多处理器一致性操作之后，增加主标签寄存器中的第一时间戳值以形成第二时间戳值。 TCUEP通过第一微处理器中的指令获取单元从多处理器系统中提取用于执行的第二指令。 TCUEP将第二指令时间戳与每个第二指令相关联。 TCUEP使得仿真清除机制能够抑制第二条指令的翻译后备缓冲区中的命中。确定第一条指令后，TCUEP完成，清除翻译后备缓冲区中的条目，并禁用仿真清除机制。

10. 发明申请

US20150095602A1 Creating A Program Product Or System For Executing A Perform Frame Management Instruction 审中-公开
标题翻译：创建执行框架管理指令的程序产品或系统
公开(公告)号：US20150095602A1
公开(公告)日：2015-04-02
申请号：US14561703
申请日：2014-12-05
申请人： International Business Machines Corporation
发明人： Dan F. Greiner , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Timothy J. Slegel , Gustav E. Sittmann
IPC分类号： G06F12/14 , G06F12/10
CPC分类号： G06F12/1475 , G06F9/30003 , G06F9/3004 , G06F9/30145 , G06F12/00 , G06F12/023 , G06F12/10 , G06F12/1027 , G06F12/145 , G06F2212/68
摘要： Creating a computer program product or a computer system to execute a frame management instruction which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.
摘要翻译：创建计算机程序产品或计算机系统以执行标识第一和第二通用寄存器的帧管理指令。第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

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