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1. 发明授权

US09330018B2 Suppressing virtual address translation utilizing bits and instruction tagging 有权
标题翻译：使用位和指令标记来抑制虚拟地址转换
公开(公告)号：US09330018B2
公开(公告)日：2016-05-03
申请号：US13776842
申请日：2013-02-26
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.
摘要翻译：一些实施例包括可以将第一物理地址存储在翻译后备缓冲器（TLB）中的第一条目中的方法。该方法可以在TLB中的第一条目中配置第一标记，以指示允许第一条目的命中抑制。该方法可以检测将导致TLB中某些条目的命中抑制的多处理器一致性操作，并导致清除TLB中某些条目。该方法可以将第二指令的第二虚拟地址转换为第二物理地址。该方法可以将第二物理地址存储在第二条目中。该方法可以在TLB中的第二条目中配置第二标记，以指示对TLB中的第二条目不允许命中抑制，并且TLB中的第二条目不允许清除。

2. 发明申请

US20150169869A1 STACK ENTRY OVERWRITE PROTECTION 有权
标题翻译：堆叠进入过度保护
公开(公告)号：US20150169869A1
公开(公告)日：2015-06-18
申请号：US14307527
申请日：2014-06-18
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Wolfgang Gellerich , Bernhard Kick , Gerrit Koch
IPC分类号： G06F21/52
CPC分类号： G06F21/52
摘要： A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.
摘要翻译：计算机处理器接收与计算机进程对应的多个执行项目。计算机处理器分配对应于第一堆栈的第一存储器部分，其中第一堆栈对应于第一类执行项目。计算机处理器分配对应于第二堆栈的第二存储器部分，其中第二堆栈对应于第二类执行项目。计算机处理器识别多个执行项目中的第一执行项目并确定对应于第一执行项目的类别。

3. 发明申请

US20150169868A1 STACK ENTRY OVERWRITE PROTECTION 有权
公开(公告)号：US20150169868A1
公开(公告)日：2015-06-18
申请号：US14108418
申请日：2013-12-17
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Wolfgang Gellerich , Bernhard Kick , Gerrit Koch
IPC分类号： G06F21/52
CPC分类号： G06F21/52
摘要： A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

4. 发明授权

US09092382B2 Reducing microprocessor performance loss due to translation table coherency in a multi-processor system 有权
标题翻译：由于多处理器系统中的转换表一致性，降低了微处理器的性能损失
公开(公告)号：US09092382B2
公开(公告)日：2015-07-28
申请号：US13667687
申请日：2012-11-02
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F13/00 , G06F13/28 , G06F12/16 , G06F13/16 , G06F12/10 , G06F12/08
CPC分类号： G06F12/16 , G06F12/08 , G06F12/0815 , G06F12/1027 , G06F13/1689 , G06F2212/1016 , G06F2212/682 , G06F2212/683
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元提取要在多处理器系统中执行的第一条指令。 TCUEP将第一个指令时间戳与每个第一个指令相关联。 TCUEP接收到多处理器一致性操作，并且在接收到多处理器一致性操作之后，增加主标签寄存器中的第一时间戳值以形成第二时间戳值。 TCUEP通过第一微处理器中的指令获取单元从多处理器系统中提取用于执行的第二指令。 TCUEP将第二指令时间戳与每个第二指令相关联。 TCUEP使得仿真清除机制能够抑制第二条指令的翻译后备缓冲区中的命中。确定第一条指令后，TCUEP完成，清除翻译后备缓冲区中的条目，并禁用仿真清除机制。

5. 发明申请

US20140129786A1 REDUCING MICROPROCESSOR PERFORMANCE LOSS DUE TO TRANSLATION TABLE COHERENCY IN A MULTI-PROCESSOR SYSTEM 有权
标题翻译：减少多处理器系统中的翻译表格的微处理器性能损失
公开(公告)号：US20140129786A1
公开(公告)日：2014-05-08
申请号：US13667687
申请日：2012-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/12
CPC分类号： G06F12/16 , G06F12/08 , G06F12/0815 , G06F12/1027 , G06F13/1689 , G06F2212/1016 , G06F2212/682 , G06F2212/683
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元提取要在多处理器系统中执行的第一条指令。 TCUEP将第一个指令时间戳与每个第一个指令相关联。 TCUEP接收多处理器一致性操作，并且在接收到多处理器一致性操作之后，增加主标签寄存器中的第一时间戳值以形成第二时间戳值。 TCUEP通过第一微处理器中的指令获取单元从多处理器系统中提取用于执行的第二指令。 TCUEP将第二指令时间戳与每个第二指令相关联。 TCUEP使得仿真清除机制能够抑制第二条指令的翻译后备缓冲区中的命中。确定第一条指令后，TCUEP完成，清除翻译后备缓冲区中的条目，并禁用仿真清除机制。

6. 发明授权

US11163579B2 Instruction generation based on selection or non-selection of a special command 有权
公开(公告)号：US11163579B2
公开(公告)日：2021-11-02
申请号：US16181839
申请日：2018-11-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joerg Deutschle , Ursel Hahn , Joerg Walter , Ernst-Dieter Weissenberger
IPC分类号： G06F9/38 , G06F11/36 , G06F11/263
摘要： Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

7. 发明申请

US20160321186A1 SUPPRESSING VIRTUAL ADDRESS TRANSLATION UTILIZING BITS AND INSTRUCTION TAGGING 有权
标题翻译：禁止使用虚拟地址翻译部分和指导标签
公开(公告)号：US20160321186A1
公开(公告)日：2016-11-03
申请号：US15145585
申请日：2016-05-03
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/1009 , G06F9/38 , G06F9/30
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元将用于第一指令的第一虚拟地址转换为第一物理地址。 TCUEP检测多处理器一致性操作，这将导致对TLB中的某些条目的打击抑制以及TLB中某些条目的清除。 TCUEP将第二指令的第二虚拟地址转换为第二物理地址，并将第二物理地址存储在TLB中的第二条目中。 TCUEP在第二个条目中配置第二个标记，以指示第二个条目不允许命中抑制，而第二个条目不允许清除。 TCUEP接收第一个地址转换请求，指示第二个条目中的命中。 TCUEP通过返回第二个物理地址来解析第一个地址转换请求。

8. 发明授权

US09330017B2 Suppressing virtual address translation utilizing bits and instruction tagging 有权
标题翻译：使用位和指令标记来抑制虚拟地址转换
公开(公告)号：US09330017B2
公开(公告)日：2016-05-03
申请号：US13667671
申请日：2012-11-02
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元将用于第一指令的第一虚拟地址转换为第一物理地址。 TCUEP检测多处理器一致性操作，这将导致对TLB中的某些条目的打击抑制以及TLB中某些条目的清除。 TCUEP将第二指令的第二虚拟地址转换为第二物理地址，并将第二物理地址存储在TLB中的第二条目中。 TCUEP在第二个条目中配置第二个标记，以指示第二个条目不允许命中抑制，而第二个条目不允许清除。 TCUEP接收第一个地址转换请求，指示第二个条目中的命中。 TCUEP通过返回第二个物理地址来解析第一个地址转换请求。

9. 发明授权

US09262626B2 Stack entry overwrite protection 有权
标题翻译：堆栈条目覆盖保护
公开(公告)号：US09262626B2
公开(公告)日：2016-02-16
申请号：US14307527
申请日：2014-06-18
申请人： International Business Machines Corporation
发明人： Joerg Deutschle , Wolfgang Gellerich , Bernhard Kick , Gerrit Koch
IPC分类号： G06F11/00 , G06F21/52
CPC分类号： G06F21/52
摘要： A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.
摘要翻译：计算机处理器接收与计算机进程对应的多个执行项目。计算机处理器分配对应于第一堆栈的第一存储器部分，其中第一堆栈对应于第一类执行项目。计算机处理器分配对应于第二堆栈的第二存储器部分，其中第二堆栈对应于第二类执行项目。计算机处理器识别多个执行项目中的第一执行项目并确定对应于第一执行项目的类别。

10. 发明申请

US20140129800A1 REDUCING MICROPROCESSOR PERFORMANCE LOSS DUE TO TRANSLATION TABLE COHERENCY IN A MULTI-PROCESSOR SYSTEM 有权
标题翻译：减少多处理器系统中的翻译表格的微处理器性能损失
公开(公告)号：US20140129800A1
公开(公告)日：2014-05-08
申请号：US13776842
申请日：2013-02-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.
摘要翻译：一些实施例包括可以将第一物理地址存储在翻译后备缓冲器（TLB）中的第一条目中的方法。该方法可以在TLB中的第一条目中配置第一标记，以指示允许第一条目的命中抑制。该方法可以检测将导致TLB中某些条目的命中抑制的多处理器一致性操作，并导致清除TLB中某些条目。该方法可以将第二指令的第二虚拟地址转换为第二物理地址。该方法可以将第二物理地址存储在第二条目中。该方法可以在TLB中的第二条目中配置第二标记，以指示对TLB中的第二条目不允许命中抑制，并且TLB中的第二条目不允许清除。

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