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1. 发明授权

US10998263B2 Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device 有权
公开(公告)号：US10998263B2
公开(公告)日：2021-05-04
申请号：US16440050
申请日：2019-06-13
申请人： International Business Machines Corporation
发明人： Jim Shih-Chun Liang , Naftali E. Lustig , Baozhen Li , Ning Lu
IPC分类号： H01L23/522 , H01L21/768
摘要： An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

2. 发明申请

US20200089836A1 CAPACITANCE EXTRACTION METHOD FOR SEMICONDUCTOR SADP METAL WIRES 审中-公开
公开(公告)号：US20200089836A1
公开(公告)日：2020-03-19
申请号：US16130693
申请日：2018-09-13
申请人： International Business Machines Corporation
发明人： Ning Lu , Calvin Bittner
IPC分类号： G06F17/50 , G03F1/70
摘要： A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique. The system and method provides a capacitance calculation and circuit simulation solution without involving use of and without computing a capacitance matrix.

3. 发明授权

US10409938B2 Method of parameter creation 有权
公开(公告)号：US10409938B2
公开(公告)日：2019-09-10
申请号：US15623549
申请日：2017-06-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric Foreman , Ning Lu , Jeffrey Hemmett
IPC分类号： G06F17/50 , G06F17/18
摘要： According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

4. 发明授权

US10393782B2 Structures and methods for RF de-embedding 有权
公开(公告)号：US10393782B2
公开(公告)日：2019-08-27
申请号：US14526596
申请日：2014-10-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert A. Groves , Ning Lu , Christopher S. Putnam , Eric Thompson
IPC分类号： G01R27/28 , G01R23/20 , G01R35/00 , H01L21/66
摘要： Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

5. 发明申请

US20190243937A1 METHOD OF PARAMETER CREATION 审中-公开
公开(公告)号：US20190243937A1
公开(公告)日：2019-08-08
申请号：US16385420
申请日：2019-04-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric Foreman , Ning Lu , Jeffrey Hemmett
IPC分类号： G06F17/50 , G06F17/18
CPC分类号： G06F17/5036 , G06F17/18 , G06F17/5045 , G06F2217/10
摘要： According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

6. 发明申请

US20170169157A1 BUILDING A CORNER MODEL OF INTERCONNECT WIRE RESISTANCE 有权
公开(公告)号：US20170169157A1
公开(公告)日：2017-06-15
申请号：US14967140
申请日：2015-12-11
申请人： International Business Machines Corporation
发明人： Ning Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5036 , G06F17/5081 , G06F2217/10
摘要： One embodiment provides a method of building a wire resistance corner model for an interconnect metal level in a semiconductor device. The method comprises determining nominal on-wafer widths and wire thicknesses at minimum and maximum design widths of the interconnect metal level, and determining standard deviations for global variations in on-wafer width and wire thickness. The method further comprises determining maximum and minimum statistical corner values for interconnect wire resistance. A first corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the maximum statistical corner values is computed. A second corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the minimum statistical corner values is computed.

7. 发明授权

US09679094B2 Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types 有权
公开(公告)号：US09679094B2
公开(公告)日：2017-06-13
申请号：US14699405
申请日：2015-04-29
申请人： International Business Machines Corporation
发明人： Ning Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036
摘要： A system, method and computer program product for determining correlation coefficient(s) among different field effect transistor types for a same electrical parameter type and/or among different electrical parameter types for a same field effect transistor type. The correlation coefficient(s) are determined based on the results of a limited number of simulation runs. Specifically, the number of simulation runs required by the disclosed embodiments is limited to one plus the product of the number of different field effect transistor types at issue, the number of different electrical parameter types at issue and the number of statistical process parameter types that impact the different electrical parameter types. Such correlation coefficient(s) can subsequently be used to develop a compact model of a semiconductor process technology. This compact model can then be used to perform variation-aware design of an integrated circuit chip.

8. 发明授权

US08972917B1 System and method for generating a field effect transistor corner model 有权
标题翻译：用于产生场效应晶体管角模型的系统和方法
公开(公告)号：US08972917B1
公开(公告)日：2015-03-03
申请号：US14037433
申请日：2013-09-26
申请人： International Business Machines Corporation
发明人： Ning Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined.
摘要翻译：公开了一种系统，方法和计算机程序产品，用于为执行目标（例如，延迟）生成场效应晶体管（FET）角模型，其精确地保留所涉及的统计模型参数之间的部分相关性（例如，信道长度，阈值电压，重叠电容等）在集成电路内的不同类型的场效应晶体管。为了实现这一点，执行初始模拟运行以确定标称性能值，所有统计模型参数设置在其标称值。然后，执行多个额外的模拟运行以确定拐角性能值。在每个连续的附加模拟运行中，不同类型的场效应晶体管的统计模型参数以相关方式偏离其标称模型参数值。然后，基于每个拐角性能值和标称性能值之间的性能差异，确定性能目标的标准偏差。

9. 发明授权

US08869085B2 Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages 有权
标题翻译：多指晶体管布局，用于减少交叉指向电气变化并充分利用可用的击穿电压
公开(公告)号：US08869085B2
公开(公告)日：2014-10-21
申请号：US13649769
申请日：2012-10-11
申请人： International Business Machines Corporation
发明人： Ning Lu
IPC分类号： G06F17/50
CPC分类号： H01L29/78 , H01L27/0207 , H01L29/41758
摘要： Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers.
摘要翻译：半导体晶体管设计的结构和方法。晶体管结构包括具有多指栅极和三个或更多个扩散区域的场效应晶体管。每个扩散区域被识别为源区域或漏极区域，并且每个扩散区域进一步被识别为内部扩散区域或外部扩散区域。在内部扩散区域和外部扩散区域中建立电接触。在外源区域内部源区域的触点大约是两倍。内部漏极区域的接触面积大约是外部漏极区域的两倍。调整每个扩散区域中的触点的数量和位置，以减少所有手指的源极节点电压与所有手指的漏极节点电压之间的差异。

10. 发明授权

US10831974B2 Capacitance extraction method for semiconductor SADP metal wires 有权
公开(公告)号：US10831974B2
公开(公告)日：2020-11-10
申请号：US16130693
申请日：2018-09-13
申请人： International Business Machines Corporation
发明人： Ning Lu , Calvin Bittner
IPC分类号： G06F30/398 , G03F1/70 , G06F30/367 , G06F30/394 , G06F119/10
摘要： A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique. The system and method provides a capacitance calculation and circuit simulation solution without involving use of and without computing a capacitance matrix.

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