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1. 发明授权

US08890732B2 Sampling circuit for ADC 有权
公开(公告)号：US08890732B2
公开(公告)日：2014-11-18
申请号：US14060510
申请日：2013-10-22
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： G11C27/024
摘要： A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC.

2. 发明申请

US20150200663A1 SAMPLE AND HOLD SWITCH CIRCUIT 有权
标题翻译：样品和保持开关电路
公开(公告)号：US20150200663A1
公开(公告)日：2015-07-16
申请号：US14487369
申请日：2014-09-16
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang , Zhengxian Zou
IPC分类号： H03K17/687
CPC分类号： H03K17/6871 , G11C11/00 , G11C27/024 , H03K17/145 , H03K17/161 , H03K2217/0054
摘要： A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.
摘要翻译：采样和保持开关电路包括时钟产生子电路，栅极电压自举单元，采样场效应晶体管，保持电容器和与信号输入端子连接的衬底选择子电路，信号输出端子和采样场效应晶体管的基板，用于根据输入的模拟信号的电压和输出的模拟信号选择信号输入端或信号输出端，与采样场效应晶体管的基板连接。采样保持开关电路降低了其栅源电压由输入信号变化引起的采样场效应晶体管的非线性，并消除了采样场效应晶体管的体积效应，从而提高了采样场效应晶体管的线性度，并扩展了动态采样保持开关电路的范围。

3. 发明申请

US20140176354A1 Sampling circuit for ADC 审中-公开
标题翻译： ADC采样电路
公开(公告)号：US20140176354A1
公开(公告)日：2014-06-26
申请号：US14060510
申请日：2013-10-22
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang
IPC分类号： H03M1/12
CPC分类号： G11C27/024
摘要： A sampling circuit for ADC includes an external input terminal, a sampling circuit and an auxiliary circuit which are connected with the external input terminal, a clock circuit and an external output terminal which are connected with the sampling circuit, and a clock feedthrough circuit connected with the auxiliary circuit, wherein the clock feedthrough circuit is respectively connected with the clock circuit and the external output terminal. The sampling circuit for ADC of the present invention decreases the impact of clock feedthrough on signal sampling, improves linearity of sampling FET, reduces harmonic distortion of the sampling circuit and improves sampling speed thereof, and improves sampling accuracy of the sampling circuit for ADC.
摘要翻译： ADC的采样电路包括与外部输入端子连接的外部输入端子，采样电路和辅助电路，与采样电路连接的时钟电路和外部输出端子，以及与采样电路连接的时钟馈通电路辅助电路，其中时钟馈通电路分别与时钟电路和外部输出端子连接。本发明的ADC采样电路降低了时钟馈通对信号采样的影响，提高了采样FET的线性度，降低了采样电路的谐波失真，提高了采样电路的采样速度，提高了ADC采样电路的采样精度。

4. 发明授权

US09379702B2 Sample and hold switch circuit 有权
标题翻译：采样保持开关电路
公开(公告)号：US09379702B2
公开(公告)日：2016-06-28
申请号：US14487369
申请日：2014-09-16
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang , Zhengxian Zou
IPC分类号： G11C27/02 , H03K5/00 , H03K17/00 , H03K17/687 , G11C11/00 , H03K17/14 , H03K17/16
CPC分类号： H03K17/6871 , G11C11/00 , G11C27/024 , H03K17/145 , H03K17/161 , H03K2217/0054
摘要： A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.
摘要翻译：采样和保持开关电路包括时钟产生子电路，栅极电压自举单元，采样场效应晶体管，保持电容器和与信号输入端子连接的衬底选择子电路，信号输出端子和采样场效应晶体管的基板，用于根据输入的模拟信号的电压和输出的模拟信号选择信号输入端或信号输出端，与采样场效应晶体管的基板连接。采样保持开关电路降低了其栅源电压由输入信号变化引起的采样场效应晶体管的非线性，并消除了采样场效应晶体管的体积效应，从而提高了采样场效应晶体管的线性度，并扩展了动态采样保持开关电路的范围。

5. 发明申请

US20150200633A1 QUICK COMPARISON CIRCUIT 有权
标题翻译：快速比较电路
公开(公告)号：US20150200633A1
公开(公告)日：2015-07-16
申请号：US14446960
申请日：2014-07-30
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang , Zhengxian Zou
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F1/0261 , H03F2200/405 , H03F2203/45394 , H03F2203/45644 , H03F2203/45728 , H03K5/2481
摘要： A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N≧2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.
摘要翻译：快速比较电路包括具有N≥2的级联N级运算放大器，翻转锁存器，偏置电路和控制信号发生电路，并且要比较的两个差分信号被输入到第一所述第N级运算放大器的输出端子与所述触发器的输入端子连接，所述偏置电路向各级运算放大器供给偏置电流，所述控制信号生成电路与所述N级运算放大器运算放大器和触发器分别为它们提供工作时间序列和复位控制信号，并且每个级运算放大器具有相同的结构。该电路具有高增益和改进的比较速度。

6. 发明申请

US20220376688A1 Power Gating Circuit 有权
公开(公告)号：US20220376688A1
公开(公告)日：2022-11-24
申请号：US17663868
申请日：2022-05-18
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang
IPC分类号： H03K17/687 , H03K17/082 , G05F3/02 , H03K19/00
摘要： A power gating circuit includes inverters and a voltage divider sub-circuit, a latch comparator, and a gated switch sub-circuit connected to an external power supply circuit of 5V, respectively. The voltage divider sub-circuit is configured to divide a voltage of 5V and output a first voltage and a second voltage to the latch comparator and the gated switch sub-circuit, both voltage values of the first voltage and the second voltage are smaller than a withstand voltage value of a field effect transistor, and the voltage value of the first voltage is greater than that of the second voltage; the latch comparator is configured to compare two signals output by the inverters and latch a comparison result; and the gated switch sub-circuit is further connected with the latch comparator to control an output voltage, thereby improving the stability of the circuit, and extending the using life of the entire circuit.

7. 发明授权

US09209765B2 Quick comparison circuit 有权
标题翻译：快速比较电路
公开(公告)号：US09209765B2
公开(公告)日：2015-12-08
申请号：US14446960
申请日：2014-07-30
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Baoding Yang , Zhengxian Zou
IPC分类号： H03K5/22 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45179 , H03F1/0261 , H03F2200/405 , H03F2203/45394 , H03F2203/45644 , H03F2203/45728 , H03K5/2481
摘要： A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N≧2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.
摘要翻译：快速比较电路包括具有N≥2的级联N级运算放大器，翻转锁存器，偏置电路和控制信号发生电路，并且要比较的两个差分信号被输入到第一所述第N级运算放大器的输出端子与所述触发器的输入端子连接，所述偏置电路向各级运算放大器供给偏置电流，所述控制信号生成电路与所述N级运算放大器运算放大器和触发器分别为它们提供工作时间序列和复位控制信号，并且每个级运算放大器具有相同的结构。该电路具有高增益和改进的比较速度。

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