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1. 发明申请

US20080163007A1 System To Detect And Identify Errors In Control Information, Read Data And/Or Write Data 有权
标题翻译：系统检测和识别控制信息中的错误，读取数据和/或写入数据
公开(公告)号：US20080163007A1
公开(公告)日：2008-07-03
申请号：US12035022
申请日：2008-02-21
申请人： Ian Shaeffer , Craig Hampel , Yuanlong Wang , Fred Ware
发明人： Ian Shaeffer , Craig Hampel , Yuanlong Wang , Fred Ware
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.
摘要翻译：集成电路，例如集成电路存储器或缓冲器件，方法和系统以及其他实施例中，分别生成对应于控制信息，写入数据和读取数据事务的多个错误代码，例如CRC代码。多个单独产生的CRC码被记录或存储在相应的存储电路中，例如循环缓冲器。对应于每个事务的存储的多个CRC码可以用于确定在特定事务期间是否发生错误，并且因此是否发出特定事务的重试。集成电路包括比较电路，用于将集成电路产生的CRC码与由控制器装置提供的CRC码进行比较。使用在读取事务期间未被使用的数据掩码信号线将对应于读取数据的CRC码传送到控制器设备。然后可以将由集成电路生成的CRC码与由控制器设备生成的CRC码进行比较，以确定是否发生错误。控制器装置产生并存储对应于控制信息，写数据和读数据的多个CRC码。然后，控制器设备将由控制器设备产生的CRC码与生成并存储在集成电路中的CRC码进行比较，以确定在特定交易期间是否发生错误。

2. 发明授权

US07836378B2 System to detect and identify errors in control information, read data and/or write data 有权
标题翻译：用于检测和识别控制信息，读取数据和/或写入数据的错误的系统
公开(公告)号：US07836378B2
公开(公告)日：2010-11-16
申请号：US12035022
申请日：2008-02-21
申请人： Ian Shaeffer , Craig Hampel , Yuanlong Wang , Fred Ware
发明人： Ian Shaeffer , Craig Hampel , Yuanlong Wang , Fred Ware
IPC分类号： G11C29/00
CPC分类号： G06F11/1004
摘要： An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.
摘要翻译：集成电路，例如集成电路存储器或缓冲器件，方法和系统以及其他实施例中，分别生成对应于控制信息，写入数据和读取数据事务的多个错误代码，例如CRC代码。多个单独产生的CRC码被记录或存储在相应的存储电路中，例如循环缓冲器。对应于每个事务的存储的多个CRC码可以用于确定在特定事务期间是否发生错误，并且因此是否发出特定事务的重试。集成电路包括比较电路，用于将集成电路产生的CRC码与由控制器装置提供的CRC码进行比较。使用在读取事务期间未被使用的数据掩码信号线将对应于读取数据的CRC码传送到控制器设备。然后可以将由集成电路生成的CRC码与由控制器设备生成的CRC码进行比较，以确定是否发生错误。控制器装置产生并存储对应于控制信息，写数据和读数据的多个CRC码。然后，控制器设备将由控制器设备产生的CRC码与生成并存储在集成电路中的CRC码进行比较，以确定在特定交易期间是否发生错误。

3. 发明授权

US08504788B2 Memory controller, system and method for read signal timing calibration 有权
标题翻译：存储器控制器，读取信号定时校准的系统和方法
公开(公告)号：US08504788B2
公开(公告)日：2013-08-06
申请号：US12520068
申请日：2007-12-19
申请人： Bret Stott , Frederick A. Ware , Ian P. Shaeffer , Yuanlong Wang
发明人： Bret Stott , Frederick A. Ware , Ian P. Shaeffer , Yuanlong Wang
IPC分类号： G06F12/00
CPC分类号： G11C7/222 , G06F13/1689 , G11C7/02 , G11C7/22
摘要： A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
摘要翻译：存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且如果由存储器控制器发出的最后读取命令之后的时间间隔超过预定值，则控制逻辑将发出补充读取命令值。

4. 发明申请

US20100039875A1 Strobe Acquisition and Tracking 有权
标题翻译：频闪采集跟踪
公开(公告)号：US20100039875A1
公开(公告)日：2010-02-18
申请号：US12520068
申请日：2007-12-19
申请人： Bret Stott , Frederick A. Ware , Ian P. Shaeffer , Yuanlong Wang
发明人： Bret Stott , Frederick A. Ware , Ian P. Shaeffer , Yuanlong Wang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/222 , G06F13/1689 , G11C7/02 , G11C7/22
摘要： A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
摘要翻译：存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且如果由存储器控制器发出的最后读取命令之后的时间间隔超过预定值，则控制逻辑将发出补充读取命令值。

5. 发明授权

US07656321B2 Signaling system 有权
标题翻译：信令系统
公开(公告)号：US07656321B2
公开(公告)日：2010-02-02
申请号：US11145264
申请日：2005-06-02
申请人： Yuanlong Wang
发明人： Yuanlong Wang
IPC分类号： H03M5/02
CPC分类号： H04L25/0272 , H01L2224/49175 , H01L2924/13091 , H01L2924/3011 , H04L25/4908 , H01L2924/00
摘要： In a signaling system, a first signal and a plurality of second signals are received via a signaling channel. A first received data value is generated in one of at least two states according to whether the first signal exceeds an average of the second signals.
摘要翻译：在信令系统中，经由信令信道接收第一信号和多个第二信号。根据第一信号是否超过第二信号的平均值，以至少两种状态之一产生第一接收数据值。

6. 发明申请

US20090249139A1 Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link 有权
标题翻译：通过双向数据链路传输的读取和写入数据的单向错误代码传输
公开(公告)号：US20090249139A1
公开(公告)日：2009-10-01
申请号：US12479684
申请日：2009-06-05
申请人： Yuanlong Wang , Frederick A. Ware
发明人： Yuanlong Wang , Frederick A. Ware
IPC分类号： G11C29/04 , G06F11/22 , H03M13/05
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

7. 发明申请

US20090249156A1 Unidirectional Error Code Transfer Method for a Bidirectional Data Link 有权
标题翻译：双向数据链路的单向错误代码传输方法
公开(公告)号：US20090249156A1
公开(公告)日：2009-10-01
申请号：US12479688
申请日：2009-06-05
申请人： Yuanlong Wang , Frederick A. Ware
发明人： Yuanlong Wang , Frederick A. Ware
IPC分类号： H03M13/09 , H04L1/08 , G06F11/10 , G06F11/14
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

8. 发明授权

US06516442B1 Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system 有权
标题翻译：可扩展对称多处理器系统中的高速缓存一致性的通道接口和协议
公开(公告)号：US06516442B1
公开(公告)日：2003-02-04
申请号：US09281749
申请日：1999-03-30
申请人： Yuanlong Wang , Brian R. Biard , Daniel Fu , Earl T. Cohen , Carl G. Amdahl
发明人： Yuanlong Wang , Brian R. Biard , Daniel Fu , Earl T. Cohen , Carl G. Amdahl
IPC分类号： H03M1300
CPC分类号： G06F12/0822 , G06F12/0813 , G06F15/17375
摘要： A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.
摘要翻译：对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。高速点对点通道将命令启动器和内存与交换机矩阵和I / O子系统耦合起来。通道的每一端连接到通道接口块（CIB）。 CIB提供了一个到该通道的逻辑接口，为另一个IC提供了一条来自CIB的通信路径。 CIB逻辑在CIB和核心逻辑之间以及CIB和Channel收发器之间呈现类似的接口。在CIB中实现了信道传输协议，以便在错误和有限缓冲的情况下将数据从一个芯片可靠地传送到另一个芯片。

9. 发明授权

US09824056B2 Handshake signaling for interface clock management 有权
公开(公告)号：US09824056B2
公开(公告)日：2017-11-21
申请号：US13503702
申请日：2010-10-29
申请人： Yuanlong Wang
发明人： Yuanlong Wang
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06 , G06F13/42 , G06F1/32
CPC分类号： G06F13/4243 , G06F1/3206 , G06F1/3237 , G06F1/3275 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

10. 发明授权

US08656254B2 Unidirectional error code transfer for both read and write data transmitted via bidirectional data link 有权
标题翻译：通过双向数据链接传输的读取和写入数据的单向错误代码传输
公开(公告)号：US08656254B2
公开(公告)日：2014-02-18
申请号：US13752324
申请日：2013-01-28
申请人： Yuanlong Wang , Frederick A. Ware
发明人： Yuanlong Wang , Frederick A. Ware
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

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