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1. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

2. 发明申请

US20100122223A1 Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics 审中-公开
标题翻译：用三维适形电介质计算电容的技术
公开(公告)号：US20100122223A1
公开(公告)日：2010-05-13
申请号：US12267599
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric input about the integrated circuit. Conductors of interest are selected from the design. Three-dimensional coupling capacitance between the selected conductors is determined. Further, a first and a second conductor can be selected from the conductors of interest. A Gaussian surface can be created around the first conductor. A random walk path can be created starting at a randomly selected point on the Gaussian surface and terminating on the second conductor. The random walk path can be used to compute the three-dimensional coupling capacitance between the first and second conductors, which can be separated from one another by multilayered dielectric media.
摘要翻译：提供了从集成电路设计中提取电容的技术。一方面，提供一种用于确定集成电路设计内的导体之间的耦合电容的方法，包括以下步骤。基于集成电路的三维技术和三维几何输入生成集成电路设计的三维表示。感兴趣的导体从设计中选出。确定所选导体之间的三维耦合电容。此外，可以从感兴趣的导体中选择第一和第二导体。可以围绕第一导体创建高斯表面。可以从高斯表面上随机选择的点开始并终止于第二导体上创建随机游走路径。随机游走路径可用于计算第一和第二导体之间的三维耦合电容，其可以通过多层电介质彼此分离。

3. 发明授权

US08239804B2 Method for calculating capacitance gradients in VLSI layouts using a shape processing engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US08239804B2
公开(公告)日：2012-08-07
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

4. 发明授权

US08122419B2 System and method for three-dimensional variational capacitance calculation 有权
标题翻译：用于三维变分电容计算的系统和方法
公开(公告)号：US08122419B2
公开(公告)日：2012-02-21
申请号：US12267598
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.
摘要翻译：提供电容提取技术。在一方面，提供了一种用于分析集成电路设计中的导体之间的变分耦合电容的方法。该方法包括以下步骤。使用一组浮动随机游走路径从设计中感兴趣的导体之间计算耦合电容。一个或多个导体受到干扰。任何受扰动影响的浮动随机行走路径都被修改。重新计算感兴趣的导体之间的耦合电容，以包括修改的浮动随机游走路径。

5. 发明申请

US20100122222A1 System and Method for Three-Dimensional Variational Capacitance Calculation 有权
标题翻译：三维变分电容计算系统与方法
公开(公告)号：US20100122222A1
公开(公告)日：2010-05-13
申请号：US12267598
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.
摘要翻译：提供电容提取技术。在一方面，提供了一种用于分析集成电路设计中的导体之间的变分耦合电容的方法。该方法包括以下步骤。使用一组浮动随机游走路径从设计中感兴趣的导体之间计算耦合电容。一个或多个导体受到干扰。任何受扰动影响的浮动随机行走路径都被修改。重新计算感兴趣的导体之间的耦合电容，以包括修改的浮动随机游走路径。

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