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1. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

2. 发明授权

US08239804B2 Method for calculating capacitance gradients in VLSI layouts using a shape processing engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US08239804B2
公开(公告)日：2012-08-07
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

3. 发明申请

US20100122223A1 Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics 审中-公开
标题翻译：用三维适形电介质计算电容的技术
公开(公告)号：US20100122223A1
公开(公告)日：2010-05-13
申请号：US12267599
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques for capacitance extraction from an integrated circuit design are provided. In one aspect, a method for determining coupling capacitance between conductors within an integrated circuit design is provided comprising the following steps. A three-dimensional representation of the integrated circuit design is generated based on three-dimensional technology and three-dimensional geometric input about the integrated circuit. Conductors of interest are selected from the design. Three-dimensional coupling capacitance between the selected conductors is determined. Further, a first and a second conductor can be selected from the conductors of interest. A Gaussian surface can be created around the first conductor. A random walk path can be created starting at a randomly selected point on the Gaussian surface and terminating on the second conductor. The random walk path can be used to compute the three-dimensional coupling capacitance between the first and second conductors, which can be separated from one another by multilayered dielectric media.
摘要翻译：提供了从集成电路设计中提取电容的技术。一方面，提供一种用于确定集成电路设计内的导体之间的耦合电容的方法，包括以下步骤。基于集成电路的三维技术和三维几何输入生成集成电路设计的三维表示。感兴趣的导体从设计中选出。确定所选导体之间的三维耦合电容。此外，可以从感兴趣的导体中选择第一和第二导体。可以围绕第一导体创建高斯表面。可以从高斯表面上随机选择的点开始并终止于第二导体上创建随机游走路径。随机游走路径可用于计算第一和第二导体之间的三维耦合电容，其可以通过多层电介质彼此分离。

4. 发明授权

US08122419B2 System and method for three-dimensional variational capacitance calculation 有权
标题翻译：用于三维变分电容计算的系统和方法
公开(公告)号：US08122419B2
公开(公告)日：2012-02-21
申请号：US12267598
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.
摘要翻译：提供电容提取技术。在一方面，提供了一种用于分析集成电路设计中的导体之间的变分耦合电容的方法。该方法包括以下步骤。使用一组浮动随机游走路径从设计中感兴趣的导体之间计算耦合电容。一个或多个导体受到干扰。任何受扰动影响的浮动随机行走路径都被修改。重新计算感兴趣的导体之间的耦合电容，以包括修改的浮动随机游走路径。

5. 发明授权

US07979825B2 Method and system for the calculation of the sensitivities of an electrical parameter of an integrated circuit 有权
标题翻译：用于计算集成电路电参数灵敏度的方法和系统
公开(公告)号：US07979825B2
公开(公告)日：2011-07-12
申请号：US12059163
申请日：2008-03-31
申请人： Ibrahim M. Elfadel , Tarek A. El Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El Moselhy
IPC分类号： G06F9/455
CPC分类号： G06F17/5018 , G06F17/5036
摘要： A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.
摘要翻译：一种用于确定可包括标称电参数值的集成电路层的电参数数据的方法和系统，以及表示标称电参数值对标称参数值变化的灵敏度的灵敏度值。从其一部分线性方程组的一部分提供层几何的模板，并使用两步法解决哪些方程，并从中确定标称电参数值。使用伴随方法从原始集合开发原始线性方程的辅助集合，并且使用两步法从辅助集合的解求出灵敏度值。

6. 发明申请

US20090248335A1 Method and System for the Calculation of the Sensitivities of an Electrical Parameter of an Integrated Circuit 有权
标题翻译：用于计算集成电路电参数灵敏度的方法和系统
公开(公告)号：US20090248335A1
公开(公告)日：2009-10-01
申请号：US12059163
申请日：2008-03-31
申请人： Ibrahim M. Elfadel , Tarek A. El Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El Moselhy
IPC分类号： G01R27/00 , G01R29/00
CPC分类号： G06F17/5018 , G06F17/5036
摘要： A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.
摘要翻译：一种用于确定可包括标称电参数值的集成电路层的电参数数据的方法和系统，以及表示标称电参数值对标称参数值变化的灵敏度的灵敏度值。从其一部分线性方程组的一部分提供层几何的模板，并使用两步法解决哪些方程，并从中确定标称电参数值。使用伴随方法从原始集合开发原始线性方程的辅助集合，并且使用两步法从辅助集合的解求出灵敏度值。

7. 发明申请

US20100122222A1 System and Method for Three-Dimensional Variational Capacitance Calculation 有权
标题翻译：三维变分电容计算系统与方法
公开(公告)号：US20100122222A1
公开(公告)日：2010-05-13
申请号：US12267598
申请日：2008-11-09
申请人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
发明人： Ibrahim M. Elfadel , Tarek A. El-Moselhy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.
摘要翻译：提供电容提取技术。在一方面，提供了一种用于分析集成电路设计中的导体之间的变分耦合电容的方法。该方法包括以下步骤。使用一组浮动随机游走路径从设计中感兴趣的导体之间计算耦合电容。一个或多个导体受到干扰。任何受扰动影响的浮动随机行走路径都被修改。重新计算感兴趣的导体之间的耦合电容，以包括修改的浮动随机游走路径。

8. 发明授权

US08495540B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 失效
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08495540B2
公开(公告)日：2013-07-23
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

9. 发明授权

US08407632B2 Detecting dose and focus variations during photolithography 失效
标题翻译：在光刻期间检测剂量和聚焦变化
公开(公告)号：US08407632B2
公开(公告)日：2013-03-26
申请号：US12881548
申请日：2010-09-14
申请人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
发明人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F7/70658
摘要： A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.
摘要翻译：在说明性实施例中提供了用于在光刻期间检测剂量和聚焦变化的方法，系统和计算机可用程序产品。在晶片上形成测试形状，该晶片用于制造集成电路，该测试形状使用为制造预定的剂量值和聚焦值形成。测量测试形状的电容。使用提取模型将电容解析为第二计量值和第二焦点值。计算给药值和第二给药值之间的差异。基于差异，建议制造中的剂量调整。

10. 发明申请

US20120290778A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20120290778A1
公开(公告)日：2012-11-15
申请号：US13557294
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.
摘要翻译：提供异构存储元件中的增加的容量，包括用于在异构存储器中存储数据的方法，该方法包括接收对应于其中至少两个存储器单元支持不同数据电平的存储器单元块的写入消息和写入地址，确定物理特性并且响应于物理特性识别与存储器单元块相关联的虚拟存储器。对每个虚拟存储器执行以下操作：生成描述虚拟存储器中的虚拟单元的约束向量; 以及响应于所述约束向量和所述写入数据计算虚拟写入向量，所述计算包括按顺序将所述写入数据逐位写入到所述虚拟存储器中，跳过已知被粘附到特定值的位置，如约束向量。虚拟写入向量被组合成写入字，并将写入字输出到存储器单元块。

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