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1. 发明授权

US09490777B2 Programmable synchronous clock divider 有权
标题翻译：可编程同步时钟分频器
公开(公告)号：US09490777B2
公开(公告)日：2016-11-08
申请号：US14617950
申请日：2015-02-10
申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
发明人： Inayat Ali , Puneet Dodeja , Sachin Jain
IPC分类号： H03K21/00 , H03K3/017 , H03K23/00 , H03K21/02 , H03K21/10
CPC分类号： H03K3/017 , H03K5/1565 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/002
摘要： A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
摘要翻译：从输入时钟信号产生分频时钟信号。通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。将比较值与计数值进行比较，以生成短和长脉冲信号。基于短脉冲信号和长脉冲信号产生分频时钟信号。分频时钟信号的占空比根据比较值而变化。

2. 发明申请

US20160233852A1 PROGRAMMABLE SYNCHRONOUS CLOCK DIVIDER 有权
标题翻译：可编程同步时钟分频器
公开(公告)号：US20160233852A1
公开(公告)日：2016-08-11
申请号：US14617950
申请日：2015-02-10
申请人： Inayat Ali , Puneet Dodeja , Sachin Jain
发明人： Inayat Ali , Puneet Dodeja , Sachin Jain
IPC分类号： H03K3/017 , H03K23/00
CPC分类号： H03K3/017 , H03K5/1565 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/002
摘要： A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.
摘要翻译：从输入时钟信号产生分频时钟信号。通过基于占空比输入的值和输入时钟信号的除法产生比较值来编程分频时钟信号的占空比。将比较值与计数值进行比较，以生成短和长脉冲信号。基于短脉冲信号和长脉冲信号产生分频时钟信号。分频时钟信号的占空比根据比较值而变化。

3. 发明授权

US08839061B2 System and method for scan chain re-ordering 有权
标题翻译：用于扫描链重新排序的系统和方法
公开(公告)号：US08839061B2
公开(公告)日：2014-09-16
申请号：US13762344
申请日：2013-02-07
申请人： Puneet Dodeja , Vishal Gupta , Manish Kumar Mittal
发明人： Puneet Dodeja , Vishal Gupta , Manish Kumar Mittal
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318583 , G06F17/505 , G06F2217/14
摘要： A system for re-ordering a scan chain of an electronic circuit design using an electronic design automation (EDA) tool includes a processor and a memory in communication with the processor. The scan chain includes a plurality of scan cells. All connections of the scan chain are disconnected. An output port of a first scan cell is connected to input ports of other scan cells to form a first set of scan cell combinations. A first scan cell combination is selected from the first set of scan cell combinations based on weighted averages of ordering parameters of each of the first set of scan cell combinations. The process is repeated to re-order the scan chain.
摘要翻译：使用电子设计自动化（EDA）工具重新排序电子电路设计的扫描链的系统包括处理器和与处理器通信的存储器。扫描链包括多个扫描单元。扫描链的所有连接都断开连接。第一扫描单元的输出端口连接到其它扫描单元的输入端口以形成第一组扫描单元组合。基于第一组扫描单元组合的排序参数的加权平均值，从第一组扫描单元组合中选择第一扫描单元组合。重复该过程以重新排序扫描链。

4. 发明申请

US20140223249A1 SYSTEM AND METHOD FOR SCAN CHAIN RE-ORDERING 有权
标题翻译：用于扫描链重新排序的系统和方法
公开(公告)号：US20140223249A1
公开(公告)日：2014-08-07
申请号：US13762344
申请日：2013-02-07
申请人： Puneet Dodeja , Vishal Gupta , Manish Kumar Mittal
发明人： Puneet Dodeja , Vishal Gupta , Manish Kumar Mittal
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318583 , G06F17/505 , G06F2217/14
摘要： A system for re-ordering a scan chain of an electronic circuit design using an electronic design automation (EDA) tool includes a processor and a memory in communication with the processor. The scan chain includes a plurality of scan cells. All connections of the scan chain are disconnected. An output port of a first scan cell is connected to input ports of other scan cells to form a first set of scan cell combinations. A first scan cell combination is selected from the first set of scan cell combinations based on weighted averages of ordering parameters of each of the first set of scan cell combinations. The process is repeated to re-order the scan chain.
摘要翻译：使用电子设计自动化（EDA）工具重新排序电子电路设计的扫描链的系统包括处理器和与处理器通信的存储器。扫描链包括多个扫描单元。扫描链的所有连接都断开连接。第一扫描单元的输出端口连接到其它扫描单元的输入端口以形成第一组扫描单元组合。基于第一组扫描单元组合的排序参数的加权平均值，从第一组扫描单元组合中选择第一扫描单元组合。重复该过程以重新排序扫描链。

5. 发明授权

US08448114B1 Method for dual edge clock and buffer tree synthesis 有权
标题翻译：双边沿时钟和缓冲树合成方法
公开(公告)号：US08448114B1
公开(公告)日：2013-05-21
申请号：US13356636
申请日：2012-01-23
申请人： Deep Gupta , Puneet Dodeja , Pankaj K. Jha
发明人： Deep Gupta , Puneet Dodeja , Pankaj K. Jha
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62 , G06F2217/84
摘要： A method for balancing both edges of a signal of an integrated circuit (IC) design includes defining a virtual cell to have the same geometry as that of a port of the IC design. First and second input pins of the virtual cell are defined for detecting rising and falling edges. The first and second input pin geometries are defined to be the same as that of the corresponding pins of the port. The virtual cell is overlapped with the port so the first and second input pins are connected to the corresponding port network. The first and second input pins are configured as sinks for clock and buffer tree synthesis. An EDA tool identifies the first and second input pins as additional parallel sinks on the port network and balances the rising and falling edges of the signal at the port.
摘要翻译：用于平衡集成电路（IC）设计的信号的两个边缘的方法包括定义具有与IC设计的端口相同的几何形状的虚拟单元。定义虚拟单元的第一和第二输入引脚用于检测上升沿和下降沿。第一和第二输入引脚几何形状被定义为与端口的相应引脚相同。虚拟单元与端口重叠，使得第一和第二输入引脚连接到相应的端口网络。第一和第二输入引脚被配置为用于时钟和缓冲器树合成的接收器。 EDA工具将第一个和第二个输入引脚识别为端口网络上的附加并行接收器，并平衡端口上信号的上升沿和下降沿。

6. 发明授权

US09053271B1 Integrated circuit reset system modification tool 有权
标题翻译：集成电路复位系统修改工具
公开(公告)号：US09053271B1
公开(公告)日：2015-06-09
申请号：US14173822
申请日：2014-02-06
申请人： Deep Gupta , Puneet Dodeja , Arvind Garg , Pankaj K. Jha
发明人： Deep Gupta , Puneet Dodeja , Arvind Garg , Pankaj K. Jha
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An electronic design automation (EDA) tool that analyzes a circuit design to identify sequential elements (flip-flops) that do not need to be reset, for example, because they do not need to be initialized in order to be in a known state, and converts the identified sequential elements to non-resettable circuits, which saves power and area.
摘要翻译：一种电子设计自动化（EDA）工具，其分析电路设计以识别不需要重置的顺序元件（触发器），例如，因为它们不需要被初始化以便处于已知状态，并将识别的顺序元件转换为不可重置电路，从而节省功率和面积。

7. 发明授权

US08645892B1 Configurable circuit and mesh structure for integrated circuit 有权
标题翻译：用于集成电路的可配置电路和网格结构
公开(公告)号：US08645892B1
公开(公告)日：2014-02-04
申请号：US13735053
申请日：2013-01-07
申请人： Vishal Gupta , Puneet Dodeja , Hans Raj Singh
发明人： Vishal Gupta , Puneet Dodeja , Hans Raj Singh
IPC分类号： G06F17/50 , H03K19/177 , H03K19/173 , H01L25/00 , G06F7/38
CPC分类号： G06F17/5077 , G06F7/38 , G06F17/5054 , G06F17/5072 , H01L23/525 , H01L25/00 , H01L27/0207 , H01L27/118 , H01L2924/0002 , H03K19/173 , H03K19/177 , H03K19/17736 , H01L2924/00
摘要： An integrated circuit (IC) design includes configurable circuits arranged in a mesh structure to facilitate routing of signals between different platforms or logic blocks within the design. Each configurable circuit has a semiconductor element with input and output terminals in a first semiconductor layer, input/output (I/O) ports corresponding to directions of the mesh structure in a second semiconductor layer, configurable input vias to allow a signal traveling in a first direction to be received, and configurable output vias that allow an output signal to be output from the configurable circuit in a second direction.
摘要翻译：集成电路（IC）设计包括以网格结构布置的可配置电路，以便于在设计中的不同平台或逻辑块之间路由信号。每个可配置电路具有在第一半导体层中具有输入和输出端子的半导体元件，对应于第二半导体层中的网状结构的方向的输入/输出（I / O）端口，可配置的输入通孔，以允许在要被接收的第一方向，以及允许在第二方向上从可配置电路输出输出信号的可配置输出通孔。

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