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1. 发明授权

US10020811B2 FPGA RAM blocks optimized for use as register files 有权
公开(公告)号：US10020811B2
公开(公告)日：2018-07-10
申请号：US15713952
申请日：2017-09-25
申请人： Microsemi SoC Corporation
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177 , G11C8/16
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

2. 发明申请

US20180191351A1 SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING 审中-公开
公开(公告)号：US20180191351A1
公开(公告)日：2018-07-05
申请号：US15848944
申请日：2017-12-20
申请人： Cypress Semiconductor Corporation
发明人： Bert Sullam , Warren Snyder , Haneef Mohammed
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/173 , H03K19/177 , H03K19/17704 , H03K19/1776
摘要： In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

3. 发明申请

US20180165396A1 LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS 审中-公开
公开(公告)号：US20180165396A1
公开(公告)日：2018-06-14
申请号：US15841326
申请日：2017-12-14
申请人： iCometrue Company Ltd.
发明人： Mou-Shiung LIN , Jin-Yuan LEE
IPC分类号： G06F17/50 , H01L27/11524 , H01L27/112 , G06F3/06 , G05B19/042 , H03K19/177 , G11C7/10
CPC分类号： G06F17/5054 , G05B19/0423 , G05B2219/15057 , G06F3/0605 , G06F3/0659 , G11C7/1012 , G11C7/1045 , G11C7/106 , G11C11/412 , H01L25/16 , H01L25/18 , H01L27/11293 , H01L27/11524 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24137 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2924/18162 , H03K19/177 , H03K19/1776
摘要： A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

4. 发明授权

US09843327B1 PSOC architecture 有权
公开(公告)号：US09843327B1
公开(公告)日：2017-12-12
申请号：US14283888
申请日：2014-05-21
申请人： Cypress Semiconductor Corporation
发明人： Warren S. Snyder , Monte Mar
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177
CPC分类号： H03K19/08 , G06F1/08 , G06F1/32 , G06F15/7867 , G06G7/06 , H03B5/364 , H03K3/012 , H03K3/014 , H03K3/02315 , H03K19/173 , H03K19/1733 , H03K19/177 , H03K19/17736 , H03K19/17748
摘要： A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

5. 发明授权

US09825635B2 Programmable logic device virtualization 有权
公开(公告)号：US09825635B2
公开(公告)日：2017-11-21
申请号：US15336640
申请日：2016-10-27
申请人： Altera Corporation
发明人： David Alexander Munday , Randall Carl Bilbrey, Jr. , Evan Custodio
IPC分类号： H03K19/177 , H04L29/06 , G06F17/50 , G06F21/76 , G06F9/445 , G06F9/50
CPC分类号： H03K19/17756 , G06F8/656 , G06F9/44505 , G06F9/5077 , G06F17/5027 , G06F17/5054 , G06F21/76 , H03K19/177 , H03K19/17728 , H03K19/1776 , H04L65/403
摘要： A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.

6. 发明授权

US09780792B2 FPGA RAM blocks optimized for use as register files 有权
公开(公告)号：US09780792B2
公开(公告)日：2017-10-03
申请号：US13898827
申请日：2013-05-21
申请人： Microsemi SoC Corporation
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177 , G11C8/16
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

7. 发明申请

US20170249412A1 Memory Controller For Heterogeneous Configurable Integrated Circuit 审中-公开
公开(公告)号：US20170249412A1
公开(公告)日：2017-08-31
申请号：US15594362
申请日：2017-05-12
申请人： Suresh Subramanian , Mukunda Krishnappa , Pohrong R. Chu , Jason Golbus , Dana L. How
发明人： Suresh Subramanian , Mukunda Krishnappa , Pohrong R. Chu , Jason Golbus , Dana L. How
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F13/1668 , G06F17/505 , G06F17/5077 , G11C7/00 , H03K19/177 , Y02D10/14
摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

8. 发明申请

US20170117899A1 Systems And Methods For Configuring An SOPC Without A Need To Use An External Memory 审中-公开
公开(公告)号：US20170117899A1
公开(公告)日：2017-04-27
申请号：US15400841
申请日：2017-01-06
申请人： Altera Corporation
发明人： Woi Jie Hooi , Kok Heng Choe
IPC分类号： H03K19/177 , G06F21/76 , G06F17/50
CPC分类号： H03K19/1776 , G06F17/5054 , G06F21/76 , H03K19/177 , H03K19/17748 , H03K19/17756
摘要： Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

9. 发明申请

US20170103157A1 STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS 有权
公开(公告)号：US20170103157A1
公开(公告)日：2017-04-13
申请号：US14879089
申请日：2015-10-08
申请人： Altera Corporation
发明人： Michael Hutton , Sean Atsatt
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F17/5068 , H03K19/177 , H03K19/17756 , H03K19/1776
摘要： In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and the distribution of certain signals including reset signals, event sampling, just to name a few.

10. 发明授权

US09558810B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09558810B2
公开(公告)日：2017-01-31
申请号：US14375748
申请日：2014-04-02
申请人： TAIYO YUDEN CO., LTD.
发明人： Masayuki Satou , Mitsunori Katsu , Hideaki Yoshida , Hiroyuki Kozutsumi
IPC分类号： G11C11/00 , G11C11/418 , G11C8/18 , G11C11/419 , H03K19/177
CPC分类号： G11C11/418 , G11C8/18 , G11C11/419 , H03K19/177
摘要： A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.
摘要翻译：一种能够重构的半导体器件，包括通过地址线或数据线彼此连接的多个逻辑单元，其中每个逻辑单元包括：多个地址线; 多条数据线; 时钟信号线，用于接收系统时钟信号; 与时钟信号同步工作的第一和第二存储单元单元; 第一地址解码器，对地址信号进行解码，并向第一存储单元单元输出解码信号; 第二地址解码器，对地址信号进行解码，并向第二存储单元单元输出解码信号; 以及地址转换检测单元，当检测到从多个地址线输入的地址信号的转变时，产生内部时钟信号并将内部时钟信号输出到第一存储单元单元，其中第一存储单元单元同步操作具有内部时钟信号，并且第二存储单元单元与系统时钟信号同步地操作。

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