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1. 发明授权

US10074729B2 Forming highly conductive source/drain contacts in III-Nitride transistors 有权
公开(公告)号：US10074729B2
公开(公告)日：2018-09-11
申请号：US15170506
申请日：2016-06-01
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L21/768 , H01L29/66 , H01L21/285 , H01L29/20 , H01L29/417 , H01L29/49 , H01L29/51 , H01L21/28 , H01L21/311 , H01L29/205 , H01L29/423 , H01L29/778 , H01L29/78
CPC分类号： H01L29/66522 , H01L21/28264 , H01L21/28587 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42376 , H01L29/4966 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/78
摘要： In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.

2. 发明授权

US09837495B2 III-nitride semiconductor structures with strain absorbing interlayers 有权
公开(公告)号：US09837495B2
公开(公告)日：2017-12-05
申请号：US14619942
申请日：2015-02-11
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L29/06 , H01L29/20 , H01L21/02 , H01L29/778 , H01L29/15 , H01L29/205
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/02488 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L29/151 , H01L29/205 , H01L29/778 , H01L29/7786
摘要： There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

3. 发明申请

US20170141192A1 Group III-V Device Structure Having a Selectively Reduced Impurity Concentration 有权
公开(公告)号：US20170141192A1
公开(公告)日：2017-05-18
申请号：US15421073
申请日：2017-01-31
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L29/20 , H01L21/02 , H01L29/66 , H01L29/778 , H01L29/15 , H01L29/207
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02389 , H01L21/02455 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/02584 , H01L21/0262 , H01L21/02634 , H01L29/1095 , H01L29/157 , H01L29/205 , H01L29/207 , H01L29/36 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/78
摘要： There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

4. 发明授权

US09461463B2 DC/DC converter with III-nitride switches 有权
标题翻译：具有III族氮化物开关的DC / DC转换器
公开(公告)号：US09461463B2
公开(公告)日：2016-10-04
申请号：US14210151
申请日：2014-03-13
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere , Jason Zhang , Bo Yang
IPC分类号： H02M3/158 , H02H7/12 , H02M1/32
CPC分类号： H02H7/1213 , H02M1/32 , H02M3/1588 , Y02B70/1466 , Y02B70/1483
摘要： Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.
摘要翻译：公开了一种降压转换器，用于将降压转换器的输入处的高电压转换为降压转换器的输出处的低电压。降压转换器包括配置成控制控制开关的占空比的控制电路，控制开关插入降压转换器的输入和输出之间。同步开关插在输出和地之间。控制开关和同步开关包括耗尽型III族氮化物晶体管。在一个实施例中，控制开关和同步开关中的至少一个包括耗尽型GaN HEMT。降压转换器还包括保护电路，其被配置为在控制电路未上电时禁止通过控制开关的电流传导。

5. 发明授权

US09449899B2 Semiconductor package with heat spreader 有权
标题翻译：半导体封装带散热器
公开(公告)号：US09449899B2
公开(公告)日：2016-09-20
申请号：US14057385
申请日：2013-10-18
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere , Chuan Cheah , Kunzhong Hu
IPC分类号： H01L23/495 , H01L23/367 , H01L23/31 , H01L23/433
CPC分类号： H01L23/495 , H01L23/3107 , H01L23/367 , H01L23/4334 , H01L23/49568 , H01L2224/16245 , H01L2224/32245 , H01L2224/73253
摘要： A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.
摘要翻译：一种半导体封装，其包括半导体管芯和散热器，所述散热器热耦合到所述半导体并且至少部分地设置在所述封装的模制外壳内。

6. 发明授权

US11605628B2 Integrated III-nitride and silicon device 有权
公开(公告)号：US11605628B2
公开(公告)日：2023-03-14
申请号：US13945276
申请日：2013-07-18
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L27/06 , H01L29/04 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/778 , H01L21/8258 , H01L29/20
摘要： A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

7. 发明申请

US20180097072A1 Group III-V Device Structure with Variable Impurity Concentration 审中-公开
公开(公告)号：US20180097072A1
公开(公告)日：2018-04-05
申请号：US15821439
申请日：2017-11-22
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L29/20 , H01L21/02 , H01L29/15 , H01L29/207 , H01L29/66 , H01L29/778
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02389 , H01L21/02455 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/02584 , H01L21/0262 , H01L21/02634 , H01L29/1095 , H01L29/157 , H01L29/205 , H01L29/207 , H01L29/36 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/78
摘要： A semiconductor structure includes a substrate, a transition body over the substrate, a group III-V intermediate body having a bottom surface over the transition body and a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a first impurity concentration at the bottom surface, a second impurity concentration at the top surface, and a variable impurity concentration that rises and falls between the bottom surface and the top surface. The first impurity concentration is greater than the second impurity concentration.

8. 发明授权

US09691889B2 Integrated power device 有权
公开(公告)号：US09691889B2
公开(公告)日：2017-06-27
申请号：US15083595
申请日：2016-03-29
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L29/66 , H01L29/778 , H01L27/06 , H01L29/20 , H01L29/205 , H01L29/417
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/778
摘要： A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.

9. 发明申请

US20160276461A1 Forming Highly Conductive Source/Drain Contacts in III-Nitride Transistors 审中-公开
标题翻译：在III型氮化物晶体管中形成高导电源/漏极触点
公开(公告)号：US20160276461A1
公开(公告)日：2016-09-22
申请号：US15170506
申请日：2016-06-01
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L29/66 , H01L21/311 , H01L29/49 , H01L21/285 , H01L29/205 , H01L29/51 , H01L29/20 , H01L21/28
CPC分类号： H01L29/66522 , H01L21/28264 , H01L21/28587 , H01L21/31111 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42376 , H01L29/4966 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/78
摘要： In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.
摘要翻译：在一个实施例中，公开了一种在III-氮化物半导体本体上制造III-氮化物晶体管的方法。该方法包括：在覆盖III-氮化物半导体主体的栅极，源极和漏极区域的场电介质中蚀刻介质沟槽，之后在栅极，源极和漏极区域上形成栅极电介质。该方法还包括在栅极介电层上形成覆盖层扩散阻挡层，然后从源极和漏极区域去除覆盖层扩散阻挡层的各个部分。此后，从源极和漏极区域去除栅极电介质以基本上暴露源极和漏极区域。然后，通过在源极和漏极区域中沉积接触金属来形成欧姆接触。该方法产生特别适用于功率晶体管的高导电源极/漏极触点，例如III型氮化物晶体管，例如GaN晶体管。在另一个实施例中，公开了一种用于高导电源极/漏极触点的结构。

10. 发明申请

US20210320103A1 III-Nitride Device 有权
公开(公告)号：US20210320103A1
公开(公告)日：2021-10-14
申请号：US17357000
申请日：2021-06-24
申请人： Infineon Technologies Americas Corp.
发明人： Michael A. Briere
IPC分类号： H01L27/06 , H01L29/04 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/778 , H01L21/8258
摘要： An integrated semiconductor device includes a silicon body that includes single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

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