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1. 发明申请

US20160284401A1 RESISTIVE MEMORY DEVICE IMPLEMENTING SELECTIVE MEMORY CELL REFRESH 审中-公开
公开(公告)号：US20160284401A1
公开(公告)日：2016-09-29
申请号：US15163534
申请日：2016-05-24
申请人： Integrated Silicon Solution, Inc.
发明人： Justin Kim , Geun-Young Park , Seong Jun Jang
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C2013/0054
摘要： A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

2. 发明授权

US09496030B2 Resistive memory device implementing selective memory cell refresh 有权
公开(公告)号：US09496030B2
公开(公告)日：2016-11-15
申请号：US15163534
申请日：2016-05-24
申请人： Integrated Silicon Solution, Inc.
发明人： Justin Kim , Geun-Young Park , Seong Jun Jang
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C2013/0054
摘要： A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

3. 发明授权

US09319038B2 Glitch free input transition detector 有权
标题翻译：无毛刺输入转换检测器
公开(公告)号：US09319038B2
公开(公告)日：2016-04-19
申请号：US14519071
申请日：2014-10-20
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang
IPC分类号： G01R29/02 , H03K5/1534 , H03K3/013 , G01R19/175 , H03K5/00
CPC分类号： H03K5/1534 , G01R19/175 , H03K3/013 , H03K2005/00136 , H03K2005/00293
摘要： A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.
摘要翻译：用于检测输入信号上的信号转换的电路包括镜像延迟电路和输入阻塞电路，以防止信号毛刺或不需要的信号脉冲被传递到输出信号节点，从而防止信号失真被检测为有效的信号转换。输入转换检测电路产生具有一致脉冲宽度的稳定且正确的转换检测脉冲。

4. 发明授权

US09373393B2 Resistive memory device implementing selective memory cell refresh 有权
标题翻译：实现选择性存储单元刷新的电阻式存储器件
公开(公告)号：US09373393B2
公开(公告)日：2016-06-21
申请号：US14297454
申请日：2014-06-05
申请人： Integrated Silicon Solution, Inc.
发明人： Justin Kim , Geun-Young Park , Seong Jun Jang
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C2013/0054
摘要： A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.
摘要翻译：电阻式存储器件实现选择刷新操作，其中只有具有减小的检测余量的存储器单元被刷新。在一些实施例中，选择性刷新操作引入感测边缘保护带，使得在读取操作期间将具有落入感测边缘保护带内的具有编程电阻的存储器单元被刷新。在存储器单元的每个读取周期，透明地执行选择性刷新操作，并且仅刷新具有减小的检测余量的存储器单元。

5. 发明授权

US09202561B1 Reference current generation in resistive memory device 有权
标题翻译：电阻存储器件中的参考电流产生
公开(公告)号：US09202561B1
公开(公告)日：2015-12-01
申请号：US14297446
申请日：2014-06-05
申请人： Integrated Silicon Solution, Inc.
发明人： Geun-Young Park , Seong Jun Jang , Justin Kim
IPC分类号： G11C13/00
CPC分类号： G11C13/0038 , G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.
摘要翻译：电阻式存储器件包括参考电流产生电路，以产生用于读出放大器的参考电流，其不受参考电阻存储器单元电阻的变化的影响。在一些实施例中，参考电流产生电路仅使用仅在低电阻状态下配置的参考电阻存储器单元。参考电流产生电路通过组合参考单元电流和偏置电流来产生参考电流。偏置电流响应于参考电流的变化由反馈电路调节，以将参考电流维持在基本上恒定的值，并且具有电流值，该电流值是高电阻状态下的电阻式存储单元的单元电流的平均值;以及低电阻状态。

6. 发明授权

US09324426B2 Method for improving sensing margin of resistive memory 有权
标题翻译：提高电阻式记忆体感应裕度的方法
公开(公告)号：US09324426B2
公开(公告)日：2016-04-26
申请号：US14293982
申请日：2014-06-02
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang , Justin Kim , Geun-Young Park
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C13/025 , G11C2013/0042 , G11C2013/0054 , G11C2013/0088 , G11C2213/16 , G11C2213/79 , G11C2213/82
摘要： A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.
摘要翻译：电阻式存储器件中的方法包括配置共享相同位线和相同源极线的阵列中的两个或更多个存储器单元并联操作为合并存储器单元; 响应于写入数据对合并的存储单元的电阻进行编程，同时对被合并的存储单元中的两个或多个电阻存储单元的电阻进行编程; 并且读取合并的存储单元的编程电阻值，同时读取合并的存储单元中的两个或多个存储单元的编程电阻。

7. 发明申请

US20150357035A1 RESISTIVE MEMORY DEVICE IMPLEMENTING SELECTIVE MEMORY CELL REFRESH 有权
标题翻译：电阻存储器件实现选择性存储器单元刷新
公开(公告)号：US20150357035A1
公开(公告)日：2015-12-10
申请号：US14297454
申请日：2014-06-05
申请人： Integrated Silicon Solution, Inc.
发明人： Justin Kim , Geun-Young Park , Seong Jun Jang
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0035 , G11C13/004 , G11C13/0069 , G11C2013/0054
摘要： A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.
摘要翻译：电阻式存储器件实现选择刷新操作，其中只有具有减小的检测余量的存储器单元被刷新。在一些实施例中，选择性刷新操作引入感测边缘保护带，使得在读取操作期间将具有落入感测边缘保护带内的具有编程电阻的存储器单元被刷新。在存储器单元的每个读取周期，透明地执行选择性刷新操作，并且仅刷新具有减小的检测余量的存储器单元。

8. 发明申请

US20150348624A1 METHOD FOR IMPROVING SENSING MARGIN OF RESISTIVE MEMORY 有权
标题翻译：改善电阻记忆体感测尺寸的方法
公开(公告)号：US20150348624A1
公开(公告)日：2015-12-03
申请号：US14293982
申请日：2014-06-02
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang , Justin Kim , Geun-Young Park
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C13/025 , G11C2013/0042 , G11C2013/0054 , G11C2013/0088 , G11C2213/16 , G11C2213/79 , G11C2213/82
摘要： A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.
摘要翻译：电阻式存储器件中的方法包括配置共享相同位线和相同源极线的阵列中的两个或更多个存储器单元并联操作为合并存储器单元; 响应于写入数据对合并的存储单元的电阻进行编程，同时对被合并的存储单元中的两个或多个电阻存储单元的电阻进行编程; 并且读取合并的存储单元的编程电阻值，同时读取合并的存储单元中的两个或多个存储单元的编程电阻。

9. 发明授权

US10331575B2 Secured chip enable with chip disable 有权
公开(公告)号：US10331575B2
公开(公告)日：2019-06-25
申请号：US15484986
申请日：2017-04-11
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang
IPC分类号： G06F12/00 , G06F12/14 , G06F21/79
摘要： A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where the memory device is disabled in response to receiving wrong passcodes repeatedly for a maximum number of tries.

10. 发明申请

US20180293181A1 SECURED CHIP ENABLE WITH CHIP DISABLE 审中-公开
公开(公告)号：US20180293181A1
公开(公告)日：2018-10-11
申请号：US15484986
申请日：2017-04-11
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang
IPC分类号： G06F12/14
CPC分类号： G06F12/1416 , G06F12/1408 , G06F12/1433 , G06F21/79 , G06F2212/1052
摘要： A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where the memory device is disabled in response to receiving wrong passcodes repeatedly for a maximum number of tries.

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