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1. 发明授权

US10366903B2 Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias 有权
公开(公告)号：US10366903B2
公开(公告)日：2019-07-30
申请号：US15575283
申请日：2015-06-26
申请人： Intel Corporation
发明人： Kevin Lin , Robert Lindsey Bristol , Alan M. Myers
IPC分类号： H01L21/32 , H01L21/3213 , H01L21/768 , H01L23/522 , H01L21/033
摘要： Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

2. 发明授权

US10147639B2 Via self alignment and shorting improvement with airgap integration capacitance benefit 有权
公开(公告)号：US10147639B2
公开(公告)日：2018-12-04
申请号：US15523330
申请日：2014-12-22
申请人： Intel Corporation
发明人： Kanwal Jit Singh , Alan M. Myers
IPC分类号： H01L21/00 , H01L23/00 , H01L21/768 , H01L29/78 , H01L21/84 , H01L21/764 , H01L23/522 , H01L23/532
摘要： A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.

3. 发明授权

US10032643B2 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme 有权
公开(公告)号：US10032643B2
公开(公告)日：2018-07-24
申请号：US15528736
申请日：2014-12-22
申请人： Intel Corporation
发明人： Jasmeet S. Chawla , Ruth A. Brain , Richard E. Schenker , Kanwal Jit Singh , Alan M. Myers
IPC分类号： H01L21/311 , H01L21/768 , H01L21/48 , H01L23/522
摘要： Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

4. 发明授权

US09887161B2 Techniques for forming interconnects in porous dielectric materials 有权
公开(公告)号：US09887161B2
公开(公告)日：2018-02-06
申请号：US15225392
申请日：2016-08-01
申请人： INTEL CORPORATION
发明人： Christopher J. Jezewski , David J. Michalak , Kanwal Jit Singh , Alan M. Myers
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768 , H01L21/3105 , H01L21/311 , H01L23/528 , H01L21/02
CPC分类号： H01L23/5329 , H01L21/02203 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/7682 , H01L21/76822 , H01L21/76826 , H01L21/76838 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

5. 发明授权

US11276581B2 Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias 有权
公开(公告)号：US11276581B2
公开(公告)日：2022-03-15
申请号：US16435240
申请日：2019-06-07
申请人： Intel Corporation
发明人： Kevin Lin , Robert Lindsey Bristol , Alan M. Myers
IPC分类号： H01L21/32 , H01L21/3213 , H01L21/768 , H01L21/033 , H01L23/522
摘要： Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

6. 发明授权

US09553018B2 Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects 有权
标题翻译：自对准通孔和插头图案化，用于后端（BEOL）互连的光触点
公开(公告)号：US09553018B2
公开(公告)日：2017-01-24
申请号：US14965734
申请日：2015-12-10
申请人： Intel Corporation
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L21/311 , H01L21/768 , H01L23/522 , H01L21/027 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.
摘要翻译：描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。介质线具有高于金属线的最上表面的最上表面。集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。介质线具有比第二光栅的金属线的最下表面低的最低表面。第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中第二光栅的线。介电材料的区域由交联的可光致发光材料组成。

7. 发明授权

US09406615B2 Techniques for forming interconnects in porous dielectric materials 有权
标题翻译：在多孔电介质材料中形成互连的技术
公开(公告)号：US09406615B2
公开(公告)日：2016-08-02
申请号：US14139970
申请日：2013-12-24
申请人： INTEL CORPORATION
发明人： Christopher J. Jezewski , David J. Michalak , Kanwal Jit Singh , Alan M. Myers
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/02203 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/7682 , H01L21/76822 , H01L21/76826 , H01L21/76838 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.
摘要翻译：公开了用于在多孔电介质材料中形成互连的技术。根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率，与互连的金属化和介电材料相比，具有高蚀刻选择性。在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。在某些情况下，可以对主介电层的介电常数（κ值），泄漏性能和/或时间依赖的介电击穿（TDDB）性能产生最小或其他可忽略的影响来进行去除和固化。一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的高多孔，超低κ（ULK）电介质材料的后端金属化的工艺。

8. 发明授权

US09379010B2 Methods for forming interconnect layers having tight pitch interconnect structures 有权
标题翻译：用于形成具有紧密间距互连结构的互连层的方法
公开(公告)号：US09379010B2
公开(公告)日：2016-06-28
申请号：US14163323
申请日：2014-01-24
申请人： Intel Corporation
发明人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/7688 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76886 , H01L21/76897 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
摘要翻译：用于在电介质层内形成具有窄间距互连结构的互连层的工艺，其中用于形成互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的潜力。本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

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