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1. 发明授权

US10025591B2 Instruction for element offset calculation in a multi-dimensional array 有权
公开(公告)号：US10025591B2
公开(公告)日：2018-07-17
申请号：US15363785
申请日：2016-11-29
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F9/30 , G06F9/355 , G06F9/38
摘要： An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.

2. 发明授权

US09619229B2 Collapsing of multiple nested loops, methods and instructions 有权
公开(公告)号：US09619229B2
公开(公告)日：2017-04-11
申请号：US13728506
申请日：2012-12-27
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30065 , G06F9/3016 , G06F9/325
摘要： In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

3. 发明授权

US09372692B2 Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality 有权
标题翻译：方法，设备，指令和逻辑，以提供带有零计数功能的置换控制
公开(公告)号：US09372692B2
公开(公告)日：2016-06-21
申请号：US13731008
申请日：2012-12-29
申请人： Intel Corporation
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3834
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：说明和逻辑提供带有零计数功能的SIMD置换控制。一些实施例包括具有多个数据字段的寄存器的处理器，每个数据字段用于存储第二多个位。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储对于相应数据字段设置为零的最重要连续位数的计数。响应于对向量前导零计数指令进行解码，执行单元对寄存器中的每个数据字段计数设置为零的最高有效连续位的数目，并将计数存储在第一目的地寄存器的相应数据字段中。向量前导零计数指令可用于生成与该组置换控制一起使用的置换控制和完成掩码，以解决采集修改散射SIMD操作中的依赖关系。

4. 发明授权

US10037208B2 Multi-element instruction with different read and write masks 有权
公开(公告)号：US10037208B2
公开(公告)日：2018-07-31
申请号：US15346531
申请日：2016-11-08
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
IPC分类号： G06F9/30 , G06F7/76
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

5. 发明授权

US11640298B2 Collapsing of multiple nested loops, methods, and instructions 有权
公开(公告)号：US11640298B2
公开(公告)日：2023-05-02
申请号：US17323409
申请日：2021-05-18
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F9/30 , G06F9/32
摘要： In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

6. 发明申请

US20180046462A1 Methods, Apparatus, Instructions and Logic to Provide Permute Controls With Leading Zero Count Functionality 有权
公开(公告)号：US20180046462A1
公开(公告)日：2018-02-15
申请号：US15790987
申请日：2017-10-23
申请人： Intel Corporation
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3834
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

7. 发明授权

US09804850B2 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality 有权
公开(公告)号：US09804850B2
公开(公告)日：2017-10-31
申请号：US15188817
申请日：2016-06-21
申请人： Intel Corporation
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3834
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

8. 发明申请

US20160335086A1 Read and Write Masks Update Instruction for Vectorization of Recursive Computations Over Independent Data 审中-公开
标题翻译：读写掩码更新指令，用于向独立数据递归计算的向量化
公开(公告)号：US20160335086A1
公开(公告)日：2016-11-17
申请号：US15219185
申请日：2016-07-25
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Christopher J. Hughes
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/3013
摘要： A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.
摘要翻译：处理器执行掩码更新指令以对第一屏蔽寄存器和第二掩码寄存器执行更新。处理器内的寄存器文件包括第一掩码寄存器和第二掩码寄存器。处理器包括执行掩膜更新指令的执行电路。响应于掩码更新指令，执行电路将反转第一掩码寄存器中给定数量的掩码位，并且还反转第二掩码寄存器中给定数量的掩码位。

9. 发明授权

US09378182B2 Vector move instruction controlled by read and write masks 有权
标题翻译：矢量移动指令由读写掩码控制
公开(公告)号：US09378182B2
公开(公告)日：2016-06-28
申请号：US13630118
申请日：2012-09-28
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Christopher Hughes
IPC分类号： G06F15/00 , G06F15/76 , G06F15/80 , G06F9/38
CPC分类号： G06F15/8084 , G06F9/3885
摘要： A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value.
摘要翻译：处理器执行向量移动指令，以在第一屏蔽寄存器和第二屏蔽寄存器的控制下将数据元素从第二向量寄存器移动到第一向量寄存器。处理器内的寄存器文件包括第一向量寄存器，第二向量寄存器，第一掩码寄存器和第二掩码寄存器。响应于向量移动指令，处理器中的执行电路是用第二向量寄存器中的给定数量的源数据元素替换第一向量寄存器中给定数量的目标数据元素。每个源数据元素对应于具有第二位值的第二掩码寄存器中的掩码位，并且其中每个目标数据元素对应于具有第一位值的第一掩码寄存器中的掩码位。

10. 发明授权

US11042377B2 Collapsing of multiple nested loops, methods, and instructions 有权
公开(公告)号：US11042377B2
公开(公告)日：2021-06-22
申请号：US16233955
申请日：2018-12-27
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F9/30 , G06F9/32
摘要： In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

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