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1. 发明申请

US20220416736A1 MULTI-CORE DIGITAL POWER AMPLIFIER WITH UNBALANCED COMBINER 有权
公开(公告)号：US20220416736A1
公开(公告)日：2022-12-29
申请号：US17359187
申请日：2021-06-25
申请人： Intel Corporation
发明人： David Ben-Haim , Ofir Degani , Assaf Ben-Bassat , Anna Nazimov , Naor Shay
IPC分类号： H03F3/24 , H03F3/60 , H03F3/189
摘要： Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.

2. 发明授权

US11592339B2 Device and method for determining a model related to a temperature shift 有权
公开(公告)号：US11592339B2
公开(公告)日：2023-02-28
申请号：US16727966
申请日：2019-12-27
申请人： Intel Corporation
发明人： Omer Sholev , Elan Banin , Ofir Degani , Assaf Ben-Bassat
IPC分类号： G01K7/00 , H04B1/04 , H04B17/13
摘要： A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

3. 发明授权

US10931384B1 Closed loop transmitter (Tx) calibration with frequency separation using a digital to time converter (DTC) 有权
公开(公告)号：US10931384B1
公开(公告)日：2021-02-23
申请号：US16727512
申请日：2019-12-26
申请人： Intel Corporation
发明人： Eli Borokhovich , Assaf Ben-Bassat , Shahar Gross , Nahum Kimiagarov
IPC分类号： H04B17/12 , H03K5/131 , H04B1/04 , H03L7/099
摘要： A closed loop transmitter (Tx) calibration system is disclosed. The closed loop Tx calibration system comprises a transmitter circuit configured to generate a Tx output signal at a Tx output frequency based on a Tx local oscillator (LO) signal. The closed loop Tx calibration system further comprises a loop back (LPBK) receiver circuit coupled to the transmitter circuit and configured to downconvert the Tx output signal at the Tx output frequency to form an LPBK baseband signal at an LPBK intermediate frequency (IF), based on an LPBK LO signal. In some embodiments, the LPBK IF frequency is different from zero. In some embodiments, the closed loop Tx calibration system further comprises an LO generation circuit configured to generate the Tx LO signal and the LPBK LO signal from a single phase locked loop (PLL) source, based on utilizing a digital to time converter (DTC) circuit.

4. 发明授权

US09927775B1 Binary stochastic time-to-digital converter and method 有权
公开(公告)号：US09927775B1
公开(公告)日：2018-03-27
申请号：US15477057
申请日：2017-04-01
申请人： Intel Corporation
发明人： Rotem Banin , Assaf Ben-Bassat , Evgeny Shumaker , Ofir Degani
IPC分类号： H03M1/50 , G04F10/00 , H03M1/04 , H03K3/037 , H03K19/23
CPC分类号： G04F10/005 , H03K19/23
摘要： A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

5. 发明申请

US20220376657A1 HIGH VOLTAGE DIGITAL POWER AMPLIFIER 有权
公开(公告)号：US20220376657A1
公开(公告)日：2022-11-24
申请号：US17323189
申请日：2021-05-18
申请人： Intel Corporation
发明人： Ofir Degani , Assaf Ben-Bassat , Ashoke Ravi , Ina Shternberg , Naor Shay
IPC分类号： H03F1/02 , H03F3/21
摘要： Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

6. 发明授权

US10958255B1 Frequency doubler pulse limiter and methods for limiting pulse widths produced by a frequency doubler 有权
公开(公告)号：US10958255B1
公开(公告)日：2021-03-23
申请号：US16727958
申请日：2019-12-27
申请人： Intel Corporation
发明人： Gil Asa , Assaf Ben-Bassat , Ofir Degani , Shahar Gross , Rotem Banin , Uri Grosglik
IPC分类号： H03K5/00 , H03K5/133 , H03K5/156 , H03K5/1534 , G01R31/3177 , G01R31/3185
摘要： This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.

7. 发明授权

US09054855B2 Synchronizing phases between local LO generation circuits 有权
标题翻译：在本地LO产生电路之间同步相位
公开(公告)号：US09054855B2
公开(公告)日：2015-06-09
申请号：US14047117
申请日：2013-10-07
申请人： Intel Corporation
发明人： Assaf Ben-Bassat
IPC分类号： H04L7/04 , H04L25/08 , H04B7/04
CPC分类号： H04L25/08 , H04B7/0413 , H04B7/0617 , H04L7/06 , H04L25/0276
摘要： Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains. A phase of each RF signal having a reference frequency in a differential mode is synchronized in each of the plurality of local LO generation circuit chains using each extracted synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode.
摘要翻译：这里一般地描述使用中央同步信号在收发机中同步链的系统和方法的实施例。在一些实施例中，在振荡器产生电路处产生具有差分模式的参考频率的RF信号和具有以公共模式除以整数的参考频率的第二频率的同步信号。具有差分模式的参考频率的RF信号和具有以公共模式除以整数的参考频率的第二频率的同步信号在多个LO线中的每一个上被提供给多个本地LO生成电路链。在多个本地LO产生电路链中提取具有以公共模式除以整数的参考频率的第二频率的每个同步信号。使用每个提取出的同步信号，在多个本地LO生成电路链中的每一个中，将具有差分模式的参考频率的每个RF信号的相位同步，其中第二频率是基准频率除以共模的整数。

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