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1. 发明申请

US20160373119A1 DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE 有权
标题翻译：数字相位控制与可编程跟踪斜率
公开(公告)号：US20160373119A1
公开(公告)日：2016-12-22
申请号：US14745326
申请日：2015-06-19
申请人： Intel Corporation
发明人： Fangxing Wei , Setul M. Shah , Michael J. Allen , Khushal N. Chandan
IPC分类号： H03L7/081 , G11C7/10
CPC分类号： H03L7/0814 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/0818
摘要： Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.
摘要翻译： I / O（输入/输出）电路中的相位补偿包括可变的可编程斜率。相位补偿电路可以对一个斜率进行相位补偿，并动态地改变相位补偿的斜率，以便更好地跟踪环境条件。相位补偿电路可以产生线性码，以施加相位补偿，以将I / O信号的相位锁定到定时信号的相位。电路用可变的可编程斜率选择性地调整线性代码，其中斜率定义了线性代码中每单位变化所施加的相位补偿量。该电路将调整后的线性码应用于锁定环路，以将I / O信号的相位锁定到定时信号的相位。

2. 发明授权

US10122526B2 Phase detector in a delay locked loop 有权
公开(公告)号：US10122526B2
公开(公告)日：2018-11-06
申请号：US15477078
申请日：2017-04-01
申请人： Intel Corporation
发明人： Fangxing Wei , Dan Shi , Michael J. Allen
IPC分类号： H04L7/033 , H04L7/027 , H04L7/04 , H03L7/087 , H04L7/00
摘要： Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

3. 发明授权

US09805773B1 Dual-range clock duty cycle corrector 有权
公开(公告)号：US09805773B1
公开(公告)日：2017-10-31
申请号：US15161908
申请日：2016-05-23
申请人： Intel Corporation
发明人： Dan Shi , Fangxing Wei , Michael J Allen
IPC分类号： H03K5/156 , G11C7/10 , H03K5/05 , G11C7/22
CPC分类号： G11C7/10 , G11C7/1072 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2211/4061 , H03K5/05 , H03K5/1565
摘要： Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

4. 发明授权

US09455726B1 XOR (exclusive or) based triangular mixing for digital phase control 有权
标题翻译：用于数字相位控制的异或（异或）三角混合
公开(公告)号：US09455726B1
公开(公告)日：2016-09-27
申请号：US14745321
申请日：2015-06-19
申请人： Intel Corporation
发明人： Fangxing Wei , Michael J Allen , Khushal N Chandan , Setul M Shah
IPC分类号： H03K3/00 , H03K3/64 , H03K3/78 , H03L7/081 , H03K19/21
CPC分类号： H03L7/0814 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03K19/21 , H03L7/0818
摘要： Phase compensation in an I/O (input/output) circuit includes a triangular control contour with a simplified generation circuit. A linear control circuit can generate a digital N-bit linear count, and route the least significant M bits [(M−1):0] for linear control for fine delay mixing of a phase compensation loop and the most significant (N−M) bits [(N−1):M] for linear control for coarse control of a delay chain for the phase compensation loop. Prior to decoding the least significant M bits for fine delay mixing, the control circuit performs a bitwise XOR (exclusive OR) of bit M with each of bits [(M−1):0] to generate M linear control bits as the linear control for fine delay mixing. The M linear control bits generate a linear control count having a triangular contour, where the linear control count continuously, repeatedly counts from 0 to (2M−1) to 0.
摘要翻译： I / O（输入/输出）电路中的相位补偿包括具有简化的生成电路的三角形控制轮廓。线性控制电路可以产生数字N位线性计数，并路由最小有效M位[（M-1）：0]用于线性控制，用于相位补偿环路的精细延迟混合和最高有效位（N-M ）位[（N-1）：M]用于相位补偿回路的延迟链的粗略控制的线性控制。在对最小有效M位解码以进行精细延迟混合之前，控制电路执行位M与位[（M-1）：0]的按位XOR（异或），以产生M个线性控制位作为线性控制用于精细延迟混合。 M个线性控制位产生具有三角形轮廓的线性控制计数，其中线性控制计数连续地从0到（2M-1）重复计数到0。

5. 发明授权

US09407273B1 Digital delay-locked loop (DLL) training 有权
标题翻译：数字延迟锁定环（DLL）训练
公开(公告)号：US09407273B1
公开(公告)日：2016-08-02
申请号：US14730514
申请日：2015-06-04
申请人： Intel Corporation
发明人： Fangxing Wei , Michael J Allen
IPC分类号： H03L7/06 , H03L7/081 , H03L7/08
CPC分类号： H03L7/0814 , H03L7/0816
摘要： A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the feedback signal with a leading edge transition in the reference clock signal. The DLL training circuit further provides an inverted feedback signal to the DLL and receives a second delay code value from the DLL that corresponds to the delay added to the inverted feedback signal to align a leading edge transition in the inverted feedback signal with a leading edge transition in the reference clock signal. The DLL selectively adds the delay code corresponding to the temporally smaller of the first delay code value or the second delay code value to the feedback signal to align the feedback signal with the reference clock signal.
摘要翻译： DLL可以包括DLL训练电路，其向DLL提供反馈信号，并且从DLL中接收对应于添加到反馈信号的延迟的第一延迟码值，以将反馈信号中的前沿转变与前沿转换参考时钟信号。 DLL训练电路还向DLL提供反向反馈信号，并从DLL中接收对应于反相反馈信号的延迟的第二延迟码值，以将反向反馈信号中的前沿跃迁与前沿转换在参考时钟信号中。该DLL选择性地将对应于第一延迟码值或第二延迟码值的时间上较小的延迟码添加到反馈信号，以使反馈信号与参考时钟信号对准。

6. 发明授权

US11018676B2 Coarse delay lock estimation for digital DLL circuits 有权
公开(公告)号：US11018676B2
公开(公告)日：2021-05-25
申请号：US16392184
申请日：2019-04-23
申请人： Intel Corporation
发明人： Fangxing Wei , Khushal Chandan , Dan Shi , Michael Allen
IPC分类号： H03L7/08 , H03L7/081 , H03L7/091 , G11C11/56 , G11C7/14 , H03L7/10
摘要： Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

7. 发明授权

US10270453B2 Coarse delay lock estimation for digital DLL circuits 有权
公开(公告)号：US10270453B2
公开(公告)日：2019-04-23
申请号：US15089523
申请日：2016-04-02
申请人： Intel Corporation
发明人： Fangxing Wei , Khushal Chandan , Dan Shi , Michael Allen
IPC分类号： H03L7/081 , H03L7/091 , G11C11/56 , G11C7/14 , H03L7/10
摘要： Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

8. 发明申请

US20170237444A1 DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE 审中-公开
公开(公告)号：US20170237444A1
公开(公告)日：2017-08-17
申请号：US15434520
申请日：2017-02-16
申请人： Intel Corporation
发明人： Fangxing Wei , Setul M. Shah , Michael J. ALLEN , Khushal N. Chandan
IPC分类号： H03L7/081 , G11C7/22 , G11C7/10
CPC分类号： H03L7/0814 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/0816 , H03L7/0818
摘要： Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.

9. 发明授权

US09548747B2 Glitch-free digitally controlled oscillator code update 有权
标题翻译：无毛刺数字控制振荡器代码更新
公开(公告)号：US09548747B2
公开(公告)日：2017-01-17
申请号：US14713174
申请日：2015-05-15
申请人： Intel Corporation
发明人： Fangxing Wei , Michael J. Allen , Setul M. Shah
IPC分类号： H03L7/085 , H03L7/099 , H03L7/095 , H03L7/087
CPC分类号： H03L7/0991 , H03L7/087 , H03L7/093 , H03L7/095 , H03L7/0995 , H03L2207/50
摘要： A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.
摘要翻译：可以通过将DCO代码更新的传送同步到DCO时钟输出信号中的脉冲的逻辑状态转换来实现无毛刺的数字控制振荡器（DCO）代码更新，使得可以在DCO延迟期间实现代码更新链条保持在相同的逻辑状态。状态机可以将DCO代码更新和脉冲更新信号提供给定时电路。 DCO代码更新可以与脉冲更新信号中的脉冲对准。定时电路可以在脉冲更新信号中的脉冲与脉冲DCO时钟输出中的脉冲的状态转换对齐时产生DCO代码更新使能信号。 DCO代码更新使能信号可以与脉冲DCO时钟输出中的状态转换对齐，以允许无毛刺的DCO代码更新。

10. 发明授权

US09166773B2 System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator 有权
公开(公告)号：US09166773B2
公开(公告)日：2015-10-20
申请号：US14590928
申请日：2015-01-06
申请人： Intel Corporation
发明人： Fangxing Wei , Subratakumar Mandal
IPC分类号： H04L7/00 , H04B1/16 , H04L1/20 , H04L7/10
CPC分类号： H04L7/0087 , H04B1/16 , H04L1/205 , H04L7/0016 , H04L7/0025 , H04L7/10
摘要： Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

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