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1. 发明授权

US10552257B2 Adaptive error correction in memory devices 有权
公开(公告)号：US10552257B2
公开(公告)日：2020-02-04
申请号：US15737202
申请日：2016-06-02
申请人： Intel Corporation
发明人： Helia Naeimi , Wei Wu , Shigeki Tomishima , Shih-Lien Lu
IPC分类号： G11C29/00 , G06F11/10 , G11C29/52 , G11C11/16 , G11C29/04
摘要： Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

2. 发明授权

US10467137B2 Apparatus, system, integrated circuit die, and method to determine when to bypass a second level cache when evicting modified data from a first level cache 有权
公开(公告)号：US10467137B2
公开(公告)日：2019-11-05
申请号：US15717934
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： Helia Naeimi , Qi Zeng
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/128 , G06F12/0888 , G06F12/084
摘要： Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

3. 发明授权

US10713052B2 Prefetcher for delinquent irregular loads 有权
公开(公告)号：US10713052B2
公开(公告)日：2020-07-14
申请号：US16021974
申请日：2018-06-28
申请人： Intel Corporation
发明人： Karthik Sankaranarayanan , Stephen J. Tarsa , Gautham N. Chinya , Helia Naeimi
IPC分类号： G06F9/38 , G06F9/30
摘要： Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.

4. 发明授权

US10423540B2 Apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line from a second memory device 有权
公开(公告)号：US10423540B2
公开(公告)日：2019-09-24
申请号：US15717933
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： Helia Naeimi , Qi Zeng
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/128 , G06F12/0891 , G06F12/0831 , G06F12/0811 , G06F12/123 , G06F12/121
摘要： Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.

5. 发明申请

US20180165152A1 ADAPTIVE ERROR CORRECTION IN MEMORY DEVICES 审中-公开
公开(公告)号：US20180165152A1
公开(公告)日：2018-06-14
申请号：US15737202
申请日：2016-06-02
申请人： Intel Corporation
发明人： Helia Naeimi , Wei Wu , Shigeki Tomishima , Shih-Lien Lu
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1048 , G11C11/1673 , G11C11/1675 , G11C29/52 , G11C2029/0411
摘要： Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

6. 发明授权

US09514796B1 Magnetic storage cell memory with back hop-prevention 有权
标题翻译：具有防跳跃功能的磁存储单元存储器
公开(公告)号：US09514796B1
公开(公告)日：2016-12-06
申请号：US14751801
申请日：2015-06-26
申请人： Intel Corporation
发明人： Charles Augustine , Shigeki Tomishima , Wei Wu , Shih-Lien Lu , James W. Tschanz , Georgios Panagopoulos , Helia Naeimi
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1677 , G11C11/1693 , G11C11/1697
摘要： An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
摘要翻译：描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。该装置还包括用于迭代地写入一个或多个比特位置的电路，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。

7. 发明授权

US09342403B2 Method and apparatus for managing a spin transfer torque memory 有权
标题翻译：用于管理自旋转移力矩存储器的方法和装置
公开(公告)号：US09342403B2
公开(公告)日：2016-05-17
申请号：US14228555
申请日：2014-03-28
申请人： Intel Corporation
发明人： David Pardo Keppel , Helia Naeimi , Jawad Nasrullah
IPC分类号： G06F11/10
CPC分类号： G06F11/106 , G06F11/1016 , G06F2212/68
摘要： An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.
摘要翻译：一种用于清洗自旋转移转矩（STT）存储器的装置和方法。例如，设备的一个实施例包括：存储器子系统，其包括至少一个自旋转移转矩（STT）存储器，STT存储器被布置成一个或多个条目; 以及擦除引擎，以确保STT的条目包含有效数据，擦洗引擎包括分析和处理逻辑，以确定每个条目是否指定的擦除间隔已过期，如果是，则使该条目或重新生效 - 从源中获取条目的数据，如果擦除间隔尚未过期，则对条目执行错误检测和/或更正。

8. 发明授权

US09858984B2 Apparatuses, methods, and systems for increasing a speed of removal of data from a memory cell 有权
公开(公告)号：US09858984B2
公开(公告)日：2018-01-02
申请号：US15389223
申请日：2016-12-22
申请人： Intel Corporation
发明人： Shih-Lien Lu , Helia Naeimi , Shigeki Tomishima
IPC分类号： G11C11/24 , G11C11/4094 , G11C11/4096 , G11C11/4074
CPC分类号： G11C11/4094 , G11C11/4072 , G11C11/4074 , G11C11/4078 , G11C11/4096
摘要： Embodiments include apparatuses and systems including a circuit which increases a speed of removal of data stored in a memory cell. In embodiments, the circuit includes a first discharge device coupled to an access transistor of a memory cell and coupled to an output terminal of a charge pump circuit to pull up a first voltage level at the output terminal to ground in response to a signal to accelerate leakage of a first leakage current; and a second discharge device coupled to a voltage generator circuit to pull down a second voltage level at a cell plate node of the memory cell to ground in response to the signal to accelerate leakage of a second leakage current, wherein the cell plate node is coupled to a storage node of the memory cell by a capacitor. Other embodiments may also be described and claimed.

9. 发明授权

US09703626B2 Recycling error bits in floating point units 有权
公开(公告)号：US09703626B2
公开(公告)日：2017-07-11
申请号：US15149988
申请日：2016-05-09
申请人： Intel Corporation , Duke University
发明人： Shih-Lien L. Lu , Helia Naeimi , Ralph Nathan , Daniel Sorin
IPC分类号： G06F7/38 , G06F9/30 , G06F11/10
CPC分类号： G06F11/10 , G06F9/3001 , G06F9/30014 , G06F9/30101
摘要： A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU. The second register is separate from the first register.

10. 发明授权

US09558807B2 Apparatuses and systems for increasing a speed of removal of data stored in a memory cell 有权
标题翻译：用于增加存储在存储单元中的数据的移除速度的装置和系统
公开(公告)号：US09558807B2
公开(公告)日：2017-01-31
申请号：US14748009
申请日：2015-06-23
申请人： Intel Corporation
发明人： Shih-Lien Lu , Helia Naeimi , Shigeki Tomishima
IPC分类号： G11C11/24 , G11C5/14 , G11C7/00 , G11C11/4096 , G11C11/4074
CPC分类号： G11C11/4094 , G11C11/4072 , G11C11/4074 , G11C11/4078 , G11C11/4096
摘要： Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.
摘要翻译：实施例包括包括可以增加存储在存储单元中的数据的移除速度的电路的装置，方法和系统。在实施例中，电路可以包括用于检测信号的控制逻辑和耦合到控制逻辑的升压电路，以允许控制逻辑响应于信号的检测来禁止升压电路的操作。放电装置可以耦合到升压电路，以响应于信号的检测而加速泄漏电流的泄漏。在本实施例中，泄漏电流是耦合到放电装置的存储单元的泄漏电流，并且加速泄漏电流的泄漏以及升压电路的操作的禁用可能增加擦除存储器中的数据的速度细胞。也可以描述和要求保护其他实施例。

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