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1. 发明申请

US20160085707A1 DUAL BUS STANDARD SWITCHING BUS CONTROLLER 审中-公开
标题翻译：双总线标准开关总线控制器
公开(公告)号：US20160085707A1
公开(公告)日：2016-03-24
申请号：US14801880
申请日：2015-07-17
申请人： Intel Corporation
发明人： Ting Lok Song , Su Wei Lim , Mikal C. Hunsaker , Hooi Kar Loo
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/385 , G06F13/387 , G06F13/4027 , G06F13/4282
摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。公开和要求保护其他实施例。

2. 发明授权

US10657092B2 Innovative high speed serial controller testing 有权
公开(公告)号：US10657092B2
公开(公告)日：2020-05-19
申请号：US15199302
申请日：2016-06-30
申请人： Intel Corporation
发明人： Lakshminarayana Pappu , Timothy J. Callahan , Hem Doshi , Hooi Kar Loo , Suketu U. Bhatt
IPC分类号： G06F13/42
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.

3. 发明授权

US09098642B2 Dual bus standard switching bus controller 有权
标题翻译：双总线标准交换总线控制器
公开(公告)号：US09098642B2
公开(公告)日：2015-08-04
申请号：US14194893
申请日：2014-03-03
申请人： Intel Corporation
发明人： Ting Lok Song , Su Wei Lim , Mikal C. Hunsaker , Hooi Kar Loo
IPC分类号： G06F13/20 , G06F13/28 , G06F13/40 , G06F13/38
CPC分类号： G06F13/4022 , G06F13/385 , G06F13/387 , G06F13/4027 , G06F13/4282
摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。公开和要求保护其他实施例。

4. 发明授权

US10229080B2 Dual bus standard switching bus controller 有权
公开(公告)号：US10229080B2
公开(公告)日：2019-03-12
申请号：US14801880
申请日：2015-07-17
申请人： Intel Corporation
发明人： Ting Lok Song , Su Wei Lim , Mikal C. Hunsaker , Hooi Kar Loo
IPC分类号： G06F13/20 , G06F13/40 , G06F13/38 , G06F13/42
摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

5. 发明授权

US11016549B2 Method, apparatus, and system for power management on a CPU die via clock request messaging protocol 有权
公开(公告)号：US11016549B2
公开(公告)日：2021-05-25
申请号：US15870629
申请日：2018-01-12
申请人： Intel Corporation
发明人： Poh Thiam Teoh , Mikal C. Hunsaker , Su Wei Lim , Gim Chong Lee , Hooi Kar Loo , Shashitheren Kerisnan , Siang Lin Tan , Ming Chew Lee , Ngeok Kuan Wai , Li Len Lim
IPC分类号： G06F1/26 , G06F1/10 , G06F13/42
摘要： Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

6. 发明申请

US20190229901A1 HARDWARE MECHANISMS FOR LINK ENCRYPTION 审中-公开
公开(公告)号：US20190229901A1
公开(公告)日：2019-07-25
申请号：US16368800
申请日：2019-03-28
申请人： Intel Corporation
发明人： Reouven Elbaz , Hooi Kar Loo , Poh Thiam Teoh , Su Wei Lim , Patrick D. Maloney , Santosh Ghosh
IPC分类号： H04L9/08 , H04L9/12 , G06F13/42
摘要： Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

7. 发明授权

US10257825B2 Reducing hardware precision time measurement inaccuracy 有权
公开(公告)号：US10257825B2
公开(公告)日：2019-04-09
申请号：US15282411
申请日：2016-09-30
申请人： Intel Corporation
发明人： Say Cheong Gan , Poh Thiam Teoh , Hooi Kar Loo , Sun Zheng E , Keng Dar Ang
IPC分类号： H04W72/04 , H04L12/26 , H04L5/00 , H04J3/06
摘要： Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a response message to the received message to the downstream device.

8. 发明授权

US09124455B1 Link equalization mechanism 有权
标题翻译：链路均衡机制
公开(公告)号：US09124455B1
公开(公告)日：2015-09-01
申请号：US14495768
申请日：2014-09-24
申请人： INTEL CORPORATION
发明人： Su Wei Lim , Ronald W. Swartz , Yueming Jiang , Hooi Kar Loo , Athourina Gevergiz , Bruce A. Tennant , Yick Yaw Ho , Poh Thiam Teoh , Jennifer Chin , Hui Shi
IPC分类号： H03H7/30 , H04L25/03
CPC分类号： H04L25/03885 , H04L25/03343 , H04L2025/03681
摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.
摘要翻译：本文描述了嵌入式高速串行接口方法的技术。这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。

9. 发明授权

US11533170B2 Hardware mechanisms for link encryption 有权
公开(公告)号：US11533170B2
公开(公告)日：2022-12-20
申请号：US16368800
申请日：2019-03-28
申请人： Intel Corporation
发明人： Reouven Elbaz , Hooi Kar Loo , Poh Thiam Teoh , Su Wei Lim , Patrick D. Maloney , Santosh Ghosh
IPC分类号： H04L9/08 , G06F13/42 , H04L9/06 , H04L9/12 , H04L9/14
摘要： Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

10. 发明申请

US20210382839A1 TIMER CONTROL FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS COMPONENTS IMPLEMENTED WITH THUNDERBOLT CONTROLLERS 有权
公开(公告)号：US20210382839A1
公开(公告)日：2021-12-09
申请号：US17412075
申请日：2021-08-25
申请人： Intel Corporation
发明人： Christopher Wing Hong Ngau , Hooi Kar Loo , Poh Thiam Teoh , Shashitheren Kerisnan , Maxim Dan , Chee Siang Chow
IPC分类号： G06F13/40 , H04B10/27 , G06F13/42
摘要： Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

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