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1. 发明授权

US11494163B2 Conversion hardware mechanism 有权
公开(公告)号：US11494163B2
公开(公告)日：2022-11-08
申请号：US16562979
申请日：2019-09-06
申请人： Intel Corporation
发明人： Naveen Mellempudi , Dipankar Das , Chunhui Mei , Kristopher Wong , Dhiraj D. Kalamkar , Hong H. Jiang , Subramaniam Maiyuran , Varghese George
IPC分类号： G06F7/499 , G06F17/16 , G06T1/20 , G06N3/04 , G06N3/08
摘要： An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

2. 发明授权

US09996347B2 Hardware apparatuses and methods relating to elemental register accesses 有权
公开(公告)号：US09996347B2
公开(公告)日：2018-06-12
申请号：US14582784
申请日：2014-12-24
申请人： Intel Corporation
发明人： Victor Lee , Ugonna Echeruo , George Chrysos , Naveen Mellempudi
IPC分类号： G06F9/30
CPC分类号： G06F9/30036
摘要： Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

3. 发明申请

US20220413803A1 SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY 有权
公开(公告)号：US20220413803A1
公开(公告)日：2022-12-29
申请号：US17304803
申请日：2021-06-25
申请人： Intel Corporation
发明人： Jorge Parra , Fangwen Fu , Subramaniam Maiyuran , Varghese George , Mike Macpherson , Supratim Pal , Chandra Gurram , Sabareesh Ganapathy , Sasikanth Avancha , Dharma Teja Vooturi , Naveen Mellempudi , Dipankar Das
IPC分类号： G06F7/544 , G06F7/523 , G06F15/80 , G06F17/16
摘要： A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.

4. 发明授权

US11468303B2 Scaling half-precision floating point tensors for training deep neural networks 有权
公开(公告)号：US11468303B2
公开(公告)日：2022-10-11
申请号：US16526376
申请日：2019-07-30
申请人： Intel Corporation
发明人： Naveen Mellempudi , Dipankar Das
IPC分类号： G06T1/20 , G06F5/01 , G06N3/063 , G06F7/487 , G06F7/544 , G06N3/04 , G06N3/08
摘要： A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations to generate loss data. The loss data is stored as a floating-point data type and scaled by a scaling factor to enable a data distribution of a gradient tensor generated based on the loss data to be represented by a 16-bit floating point data type.

5. 发明授权

US11507815B2 Scaling half-precision floating point tensors for training deep neural networks 有权
公开(公告)号：US11507815B2
公开(公告)日：2022-11-22
申请号：US17742138
申请日：2022-05-11
申请人： Intel Corporation
发明人： Naveen Mellempudi , Dipankar Das
IPC分类号： G06T1/20 , G06F5/01 , G06N3/063 , G06F7/487 , G06F7/544 , G06N3/04 , G06N3/08
摘要： A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations. The functional units can also include circuitry to analyze statistics for output values of the tensor computations, determine a target format to convert the output values, the target format determined based on the statistics for the output values and a precision associated with a second layer of the neural network, and convert the output values to the target format.

6. 发明申请

US20220206805A1 INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 有权
公开(公告)号：US20220206805A1
公开(公告)日：2022-06-30
申请号：US17134353
申请日：2020-12-26
申请人： Intel Corporation
发明人： Alexander Heinecke , Naveen Mellempudi , Robert Valentine , Mark Charney , Christopher Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30 , G06F7/499 , H03M7/24
摘要： Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

7. 发明申请

US20160188334A1 HARDWARE APPARATUSES AND METHODS RELATING TO ELEMENTAL REGISTER ACCESSES 有权
标题翻译：硬件设备和与元件寄存器访问相关的方法
公开(公告)号：US20160188334A1
公开(公告)日：2016-06-30
申请号：US14582784
申请日：2014-12-24
申请人： Intel Corporation
发明人： Victor Lee , Ugonna Echeruo , George Chrysos , Naveen Mellempudi
IPC分类号： G06F9/30
CPC分类号： G06F9/30036
摘要： Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.
摘要翻译：描述与具有具有基本偏移的寄存器操作数的向量指令相关的方法和装置。在一个实施例中，硬件处理器包括解码单元，用于对具有基本偏移量的寄存器操作数解码向量指令，以访问由寄存器操作数指定的寄存器中的第一数量的元素，其中第一个数字是元素的总数在所述寄存器中减去所述元素偏移量，访问下一逻辑寄存器中的第二数量的元素，其中所述第二数量是所述元素偏移量，并且将所述第一数量的元素和所述第二数量的元素组合为数据向量，以及执行单元来执行数据向量的向量指令。

8. 发明授权

US11501139B2 Scaling half-precision floating point tensors for training deep neural networks 有权
公开(公告)号：US11501139B2
公开(公告)日：2022-11-15
申请号：US15869582
申请日：2018-01-12
申请人： Intel Corporation
发明人： Naveen Mellempudi , Dipankar Das
IPC分类号： G06T1/20 , G06F5/01 , G06N3/063 , G06F7/487 , G06F7/544 , G06N3/04 , G06N3/08
摘要： One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.

9. 发明申请

US20220206801A1 APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS 有权
公开(公告)号：US20220206801A1
公开(公告)日：2022-06-30
申请号：US17134373
申请日：2020-12-26
申请人： Intel Corporation
发明人： Naveen Mellempudi , Alexander F. Heinecke , Robert Valentine , Mark J. Charney , Christopher J. Hughes , Evangelos Georganas , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30 , G06F7/499 , G06F9/38
摘要： Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.

10. 发明授权

US11321805B2 Dynamic precision management for integer deep learning primitives 有权
公开(公告)号：US11321805B2
公开(公告)日：2022-05-03
申请号：US17083588
申请日：2020-10-29
申请人： Intel Corporation
发明人： Naveen Mellempudi , Dheevatsa Mudigere , Dipankar Das , Srinivas Sridharan
IPC分类号： G06T1/20 , G06N3/063 , G06F17/16 , G06F7/523 , G06F5/01 , G06F7/501 , G06F17/15 , G06N3/04 , G06F7/544 , G06N3/08
摘要： One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

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