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1. 发明申请

US20230111292A1 METHOD FOR PROCESSING DATA SETS CONTAINING AT LEAST ONE TIME SERIES, DEVICE FOR CARRYING OUT, VEHICLE AND COMPUTER PROGRAM 有权
公开(公告)号：US20230111292A1
公开(公告)日：2023-04-13
申请号：US17905439
申请日：2021-02-12
申请人： VOLKSWAGEN AKTIENGESELLSCHAFT
发明人： Jan PIEWEK , Konstantin JONAS
IPC分类号： G06F7/483 , G06F5/01
摘要： A method for processing data sets having at least one time series. These are measurement values of sensors that are sensed at certain times. The data of the measured values and the respective times at which the data were sensed are stored as data elements of the time series. The method compresses the data set by rounding the sensed data with subsequent decimation of the data elements of the data set which are contained in the time series.

2. 发明授权

US11625601B2 Neural network method and apparatus 有权
公开(公告)号：US11625601B2
公开(公告)日：2023-04-11
申请号：US16564494
申请日：2019-09-09
申请人： Samsung Electronics Co., Ltd.
发明人： Changyong Son , Jinwoo Son , Byungin Yoo , Chang Kyu Choi , Jae-Joon Han
IPC分类号： G06N3/08 , G06N3/063 , G06N3/082 , G06F5/01 , G06F7/523 , G06N3/04
摘要： A lightened neural network, method, and apparatus, and recognition method and apparatus implementing the same. A neural network includes a plurality of layers each comprising neurons and plural synapses connecting neurons included in neighboring layers. Synaptic weights with values greater than zero and less than a preset value of a variable a, which is greater than zero, may be at least partially set to zero. Synaptic weights with values greater than a preset value of a variable b, which is greater than zero, may be at least partially set to the preset value of the variable b.

3. 发明授权

US11614919B2 Circuit 有权
公开(公告)号：US11614919B2
公开(公告)日：2023-03-28
申请号：US16992421
申请日：2020-08-13
申请人： Realtek Semiconductor Corporation
发明人： Szu-Chun Chang
IPC分类号： G06F7/523 , G06F5/01 , H03K19/21
摘要： A circuit, comprising a first term operation circuit and a second term operation circuit, a third term operation circuit, and a second calculation circuit. Each of the first and the second term operation circuits comprises multiple higher bit operation circuits, a lowest bit operation circuit, and a first calculation circuit. Each of the higher bit operation circuits selectively left-shifts a multiplicand by different bits, outputs the shifted multiplicand, determines a sign of the shifted multiplicand, and left-shifts the shifted multiplicand. The lowest bit operation circuit outputs the multiplicand, and determines a sign of the multiplicand. The first calculation circuit generates a term operation result. The third term operation circuit generates a third term operation result. The second calculation circuit adds the term operation result of the first and second term operation circuits and the third term operation result to generate a total operation result.

4. 发明申请

US20230055513A1 Reconfigurable Processor Circuit Architecture 有权
公开(公告)号：US20230055513A1
公开(公告)日：2023-02-23
申请号：US17967173
申请日：2022-10-17
申请人： Cornami, Inc.
发明人： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC分类号： G06F15/80 , G06F9/30 , G06F9/38 , G06F9/54 , G06F7/52 , G06F5/01 , G06F9/48 , G06F7/50 , G06F7/544 , H03K19/21 , G06F7/523 , G06F7/487
摘要： A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

5. 发明授权

US11586896B2 In-memory computing architecture and methods for performing MAC operations 有权
公开(公告)号：US11586896B2
公开(公告)日：2023-02-21
申请号：US16908210
申请日：2020-06-22
申请人： Infineon Technologies LLC
发明人： Ramesh Chettuvetty , Vijay Raghavan , Hans Van Antwerpen
IPC分类号： G06N3/063 , G06N3/04 , G06F7/544 , G11C11/54 , G11C11/56 , G06F5/01 , H03M1/38
摘要： In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

6. 发明授权

US11573766B2 Floating point to fixed point conversion 有权
公开(公告)号：US11573766B2
公开(公告)日：2023-02-07
申请号：US17141284
申请日：2021-01-05
申请人： Imagination Technologies Limited
发明人： Kenneth Rovers
IPC分类号： G06F5/01 , H03M7/24 , G06F7/48
摘要： A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1),bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

7. 发明授权

US11568020B1 System and methods for network sensitivity analysis 有权
公开(公告)号：US11568020B1
公开(公告)日：2023-01-31
申请号：US16268508
申请日：2019-02-06
申请人： SNO, Inc.
发明人： G. Edward Powell , Mark T. Lane , Stephen C. Bedard , N. Edward White
IPC分类号： G06F15/16 , G06F17/16 , H04L41/14 , G06N20/00 , G06F5/01
摘要： A computer-implemented method to establish a relative importance of an input parameter pj in a plurality of input parameters pi in a data set input to a machine learning model, the data set represented by a j row by k column matrix Im, an intersection of each row with each column defining an element, the method includes for each of the plurality of parameters pi in the input data set, a computer sorts columns ki of the matrix Im. to produce a re-ordered matrix Im,j; the computer determines a hyper-parameter N* of sub-matrices into which may be sorted the values in a jth row of the re-ordered matrix Im,j; the computer generates a plurality of group sub-matrices Gi, each of the group sub-matrices comprising a subset of columns and the jth row; the computer inputs the re-ordered matrix Im,j into a fully-trained machine learning model to produce machine learning model outputs; and the computer produces normalized mean values of the outputs.

8. 发明授权

US11562201B2 Neural network layer processing with normalization and transformation of data 有权
公开(公告)号：US11562201B2
公开(公告)日：2023-01-24
申请号：US16284445
申请日：2019-02-25
申请人： Microsoft Technology Licensing, LLC
发明人： Daniel Lo
IPC分类号： G06N3/00 , G06N3/04 , G06F5/01 , G06N3/08
摘要： Processors and methods for neural network processing are provided. A method includes receiving a subset of data corresponding to a layer of a neural network for processing using the processor. The method further includes during a forward propagation pass: (1) normalizing the subset of the data corresponding to the layer of the neural network based on an average associated with the subset of the data and a variance associated with the subset of the data, where the normalizing the subset of the data comprises dynamically updating the average and dynamically updating the variance, to generate normalized data and (2) applying a transformation to the normalized data using a fixed scale parameter corresponding to the subset of the data and a fixed shift parameter corresponding to the subset of the data such that during the forward propagation pass neither the fixed scale parameter nor the fixed shift parameter is updated.

9. 发明申请

US20220381584A1 EXTENSIBLE ENVIRONMENTAL DATA COLLECTION PACK 有权
公开(公告)号：US20220381584A1
公开(公告)日：2022-12-01
申请号：US17884163
申请日：2022-08-09
申请人： GrayWolf Sensing Solutions LLC
发明人： William F. VanWart , Richard T. Stonier , John Coffey
IPC分类号： G01D4/00 , G06F5/01
摘要： An environmental data collection system includes one or more smart sensors, a controller coupled to the one or more smart sensors, the controller including one or more modular decoders having a processor and a memory storing computer readable program code, that when executed by the processor, causes the modular decoder to configure communication and data retrieval between the one or more smart sensors and the controller, perform signal processing on data retrieved from the one or more smart sensors specific to the sensing capabilities of the one or more smart sensors, convert the signal processed data to a fixed bit format, and convey the fixed bit data to the controller.

10. 发明授权

US11514291B2 Neural network processing element incorporating compute and local memory elements 有权
公开(公告)号：US11514291B2
公开(公告)日：2022-11-29
申请号：US15943976
申请日：2018-04-03
申请人： Hailo Technologies Ltd.
发明人： Avi Baum , Or Danon , Hadar Zeitlin , Daniel Ciubotariu , Rami Feig
IPC分类号： G06N3/063 , G06N3/04 , G06F12/02 , G06F12/06 , G06N20/00 , G06F30/30 , G06F30/27 , G06V10/40 , G06F7/501 , G06F7/523 , G06F9/50 , G06F17/10 , G06F5/01 , G06N3/08 , G06F13/16 , G06F9/30 , G06K9/62 , G06N3/02
摘要： A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

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