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1. 发明授权

US11048587B2 Apparatus and method for detecting and recovering from data fetch errors 有权
公开(公告)号：US11048587B2
公开(公告)日：2021-06-29
申请号：US16292085
申请日：2019-03-04
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/14 , G06F11/10
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

2. 发明申请

US20160103785A1 GATHER USING INDEX ARRAY AND FINITE STATE MACHINE 有权
公开(公告)号：US20160103785A1
公开(公告)日：2016-04-14
申请号：US14881111
申请日：2015-10-12
申请人： Intel Corporation
发明人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F15/80 , G06F9/30
CPC分类号： G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

3. 发明授权

US10725755B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US10725755B2
公开(公告)日：2020-07-28
申请号：US15615798
申请日：2017-06-06
申请人： Intel Corporation
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffrey J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F8/41 , G06F9/38 , G06F9/54 , G06F11/36
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

4. 发明申请

US20200004633A1 APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS 审中-公开
公开(公告)号：US20200004633A1
公开(公告)日：2020-01-02
申请号：US16292085
申请日：2019-03-04
申请人： Intel Corporation
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/14 , G06F11/10
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

5. 发明授权

US09720843B2 Access type protection of memory reserved for use by processor logic 有权
公开(公告)号：US09720843B2
公开(公告)日：2017-08-01
申请号：US13729439
申请日：2012-12-28
申请人： Intel Corporation
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Hisham Shafi , Alex Berenzon , Geoffrey S. Strongin , Iris Sorani
IPC分类号： G06F12/00 , G06F12/1027 , G06F12/14
CPC分类号： G06F12/1027 , G06F12/1441 , G06F12/145 , G06F2212/1052
摘要： A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

6. 发明授权

US09524240B2 Obscuring memory access patterns in conjunction with deadlock detection or avoidance 有权
公开(公告)号：US09524240B2
公开(公告)日：2016-12-20
申请号：US13782416
申请日：2013-03-01
申请人： Intel Corporation
发明人： Shay Gueron , Gad Sheaffer , Shlomo Raikin
IPC分类号： G06F12/14 , G06F12/08 , G06F21/55 , H04L9/00
CPC分类号： G06F12/0808 , G06F12/0802 , G06F21/556 , G06F2201/885 , G06F2212/1052 , H04L9/003
摘要： Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

7. 发明授权

US09753889B2 Gather using index array and finite state machine 有权
公开(公告)号：US09753889B2
公开(公告)日：2017-09-05
申请号：US14881111
申请日：2015-10-12
申请人： Intel Corporation
发明人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F12/02 , G06F15/80 , G06F9/30 , G06F9/345
CPC分类号： G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

8. 发明申请

US20170192934A1 GATHER USING INDEX ARRAY AND FINITE STATE MACHINE 审中-公开
公开(公告)号：US20170192934A1
公开(公告)日：2017-07-06
申请号：US14616323
申请日：2015-02-06
申请人： Intel Corporation
发明人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

9. 发明申请

US20160170900A1 VIRTUAL MEMORY ADDRESS RANGE REGISTER 审中-公开
标题翻译：虚拟内存地址范围注册
公开(公告)号：US20160170900A1
公开(公告)日：2016-06-16
申请号：US15048400
申请日：2016-02-19
申请人： Intel Corporation
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

10. 发明申请

US20150074373A1 SCATTER USING INDEX ARRAY AND FINITE STATE MACHINE 有权
标题翻译：散射器使用索引阵列和有限状态机
公开(公告)号：US20150074373A1
公开(公告)日：2015-03-12
申请号：US13977727
申请日：2012-06-02
申请人： INTEL CORPORATION
发明人： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Levy Ofer
IPC分类号： G06F15/78 , G06F9/30
CPC分类号： G06F15/7839 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3808 , G06F9/383
摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
摘要翻译：公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。索引数组保存一组索引和一组对应的掩码元素。有限状态机有助于散射操作。地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。正在生成的每组地址的缓冲区中分配存储空间。与生成的地址集相对应的数据元素被复制到缓冲器。如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。

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