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1. 发明申请

US20140169062A1 Methods of Manufacturing Embedded Bipolar Switching Resistive Memory 有权
标题翻译：嵌入式双极开关电阻式存储器的制造方法
公开(公告)号：US20140169062A1
公开(公告)日：2014-06-19
申请号：US13714173
申请日：2012-12-13
申请人： INTERMOLECULAR, INC.
发明人： Mankoo Lee , Tony Chiang , Dipankar Pramanik
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L29/785 , H01L29/868 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.
摘要翻译：非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻低电压区域。此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。

2. 发明授权

US08524528B2 Methods for forming resistive-switching metal oxides for nonvolatile memory elements 有权
公开(公告)号：US08524528B2
公开(公告)日：2013-09-03
申请号：US13725574
申请日：2012-12-21
申请人： Intermolecular Inc.
发明人： Sean Barstow , Tony Chiang , Pragati Kumar , Sandra Malhotra
IPC分类号： H01L21/00 , H01L21/16 , H01L21/20 , H01L21/36
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

3. 发明授权

US10580978B2 Current compliance layers and memory arrays comprising thereof 有权
公开(公告)号：US10580978B2
公开(公告)日：2020-03-03
申请号：US15863199
申请日：2018-01-05
申请人： Intermolecular, Inc.
发明人： Tony Chiang , Sergey V Barabash , Karl Littau , Vijay Kris Narasimhan , Stephen Weeks
IPC分类号： H01L45/00 , H01L27/24
摘要： Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

4. 发明申请

US20180198064A1 Current Compliance Layers and Memory Arrays Comprising Thereof 审中-公开
公开(公告)号：US20180198064A1
公开(公告)日：2018-07-12
申请号：US15863199
申请日：2018-01-05
申请人： Intermolecular, Inc.
发明人： Tony Chiang , Sergey V Barabash , Karl Littau , Vijay Kris Narasimhan , Stephen Weeks
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , G11C13/0007 , G11C13/003 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1246 , H01L45/144 , H01L45/16 , H01L45/1608
摘要： Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

5. 发明授权

US08901708B2 Yttrium and titanium high-k dielectric films 有权
公开(公告)号：US08901708B2
公开(公告)日：2014-12-02
申请号：US13675971
申请日：2012-11-13
申请人： Intermolecular, Inc.
发明人： Imran Hashim , Hanhong Chen , Tony Chiang , Indranil De , Nobumichi Fuchigami , Edward Haywood , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/02 , H01L49/02 , C23C16/40 , C23C16/455 , H01L21/314 , H01L21/316 , H01L27/108
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

6. 发明申请

US20130338305A1 Methods for Coating a Substrate with an Amphiphilic Compound 有权
公开(公告)号：US20130338305A1
公开(公告)日：2013-12-19
申请号：US13971613
申请日：2013-08-20
申请人： Intermolecular, Inc.
发明人： Anh Duong , Tony Chiang , Zachary M. Fresco , Nitin Kumar , Chi-I Lang , Jinhong Tong , Anna Tsizelmon
IPC分类号： C09D129/04
CPC分类号： H01L23/5329 , C09D129/04 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

7. 发明申请

US20130071990A1 Yttrium and Titanium High-K Dielectric Films 有权
标题翻译：钇和钛高K介电薄膜
公开(公告)号：US20130071990A1
公开(公告)日：2013-03-21
申请号：US13677126
申请日：2012-11-14
申请人： Intermolecular, Inc.
发明人： Imran Hashim , Hanhong Chen , Tony Chiang , Indranil De , Nobi Fuchigami , Edward Haywood , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/02
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产氧化物层反应。

8. 发明申请

US20130069201A1 Yttrium and Titanium High-K Dielectric Films 有权
公开(公告)号：US20130069201A1
公开(公告)日：2013-03-21
申请号：US13675971
申请日：2012-11-13
申请人： Intermolecular, Inc.
发明人： Imran Hashim , Hanhong Chen , Tony Chiang , Indranil De , Nobumichi Fuchigami , Edward Haywood , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L49/02
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

9. 发明授权

US09076523B2 Methods of manufacturing embedded bipolar switching resistive memory 有权
标题翻译：嵌入式双极性开关电阻存储器的制造方法
公开(公告)号：US09076523B2
公开(公告)日：2015-07-07
申请号：US13714173
申请日：2012-12-13
申请人： Intermolecular, Inc.
发明人： Mankoo Lee , Tony Chiang , Dipankar Pramanik
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L29/785 , H01L29/868 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.
摘要翻译：非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻低电压区域。此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。

10. 发明授权

US08742392B2 Bipolar multistate nonvolatile memory 有权
标题翻译：双极多态非易失性存储器
公开(公告)号：US08742392B2
公开(公告)日：2014-06-03
申请号：US13953296
申请日：2013-07-29
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Tony Chiang
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616
摘要： Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含通过使用多层可变电阻层而具有改进的器件开关容量的电阻式开关存储器元件。在一个实施例中，电阻式开关元件包括至少三层可变电阻材料以增加逻辑状态的数量。每个可变电阻层可以具有相关联的高电阻状态和相关联的低电阻状态。由于每个可变电阻层的电阻决定了存储的数字数据位，每个存储元件的多个可变电阻层允许额外的数据存储，而不需要进一步增加非易失性存储器件的密度。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

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