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1. 发明授权

US10381098B2 Memory interface latch with integrated write-through and fence functions 有权
公开(公告)号：US10381098B2
公开(公告)日：2019-08-13
申请号：US15823640
申请日：2017-11-28
申请人： International Business Machines Corporation
发明人： Elizabeth L. Gerhard , Todd A. Christensen , Chad A. Adams , Peter T. Freiburger
IPC分类号： G11C29/38 , G11C7/10 , G11C29/36 , G06F17/50 , H03K19/20
摘要： A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

2. 发明申请

US20190164623A1 MEMORY INTERFACE LATCH WITH INTEGRATED WRITE-THROUGH AND FENCE FUNCTIONS 审中-公开
公开(公告)号：US20190164623A1
公开(公告)日：2019-05-30
申请号：US15823640
申请日：2017-11-28
申请人： International Business Machines Corporation
发明人： Elizabeth L. Gerhard , Todd A. Christensen , Chad A. Adams , Peter T. Freiburger
IPC分类号： G11C29/38 , G11C7/10 , G11C29/36
CPC分类号： G11C29/38 , G06F17/5022 , G06F2217/12 , G11C7/106 , G11C29/02 , G11C29/1201 , G11C29/36 , H03K19/20
摘要： A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

3. 发明授权

US10229748B1 Memory interface latch with integrated write-through function 有权
公开(公告)号：US10229748B1
公开(公告)日：2019-03-12
申请号：US15823635
申请日：2017-11-28
申请人： International Business Machines Corporation
发明人： Elizabeth L. Gerhard , Todd A. Christensen , Chad A. Adams , Peter T. Freiburger
IPC分类号： G11C7/10 , G11C29/38 , G11C29/12
摘要： A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

4. 发明申请

US20150131368A1 IMPLEMENTING SENSE AMPLIFIER FOR SENSING LOCAL WRITE DRIVER WITH BOOTSTRAP WRITE ASSIST FOR SRAM ARRAYS 有权
标题翻译：用于感应本地写入驱动器的感应放大器与用于SRAM阵列的BOOTSTRAP写入辅助
公开(公告)号：US20150131368A1
公开(公告)日：2015-05-14
申请号：US14077559
申请日：2013-11-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Chad A. Adams , Elizabeth L. Gerhard , Jeffrey M. Scherer
IPC分类号： G11C11/419 , G06F17/50
CPC分类号： G11C11/419 , G06F17/5063 , G06F17/5068
摘要： A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.
摘要翻译：一种用于实现用于感测本地写入驱动器的读出放大器的方法和电路，其具有用于静态随机存取存储器（SRAM）阵列的自举写入辅助，以及提供主题电路所在的设计结构。该电路包括用于读写操作的读写放大器与写辅助升压电路。读出放大器在选定的SRAM单元列处捕获并放大写入数据，并将写入数据驱动到局部位线上。写入辅助升压电路在写入操作期间临时向SRAM单元提供增加的器件电压差，以显着提高SRAM单元写入能力。

5. 发明申请

US20140149818A1 DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY 审中-公开
公开(公告)号：US20140149818A1
公开(公告)日：2014-05-29
申请号：US13786629
申请日：2013-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Elizabeth L. Gerhard , Michael W. Harper , Jesse D. Smith
IPC分类号： G01R31/3177
CPC分类号： G11C29/12015 , G11C29/32
摘要： A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space.

6. 发明申请

US20140092700A1 FINE GRANULARITY POWER GATING 有权
标题翻译：精细粒度功率增益
公开(公告)号：US20140092700A1
公开(公告)日：2014-04-03
申请号：US13633217
申请日：2012-10-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Chad A. Adams , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C8/10 , G11C5/147 , G11C8/08 , G11C8/12
摘要： Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage.
摘要翻译：存储器阵列的行被分割成预定数量的字线组。字线组中的每一行都具有设置在并行电源线之间的字线。字线组中的一行中的每个电源线由字线组中的相邻行共享。字线组的边界上的行具有由相邻字线组的边界上的行共享的电源线。响应于由字线选择的字线组中的一行，字线组中的所有电源线处于全电源电压。相邻字线组中的大多数电源线处于全电源电压。其他字线组中的所有电源线都处于电源门控电压。

7. 发明授权

US10916323B2 Memory interface latch with integrated write-through and fence functions 有权
公开(公告)号：US10916323B2
公开(公告)日：2021-02-09
申请号：US16449778
申请日：2019-06-24
申请人： International Business Machines Corporation
发明人： Elizabeth L. Gerhard , Todd A. Christensen , Chad A. Adams , Peter T. Freiburger
IPC分类号： G11C29/38 , G11C29/36 , G11C7/10 , G11C29/12 , G11C29/02 , G06F30/30 , H03K19/20 , G06F30/33 , G06F119/18
摘要： A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

8. 发明授权

US09251869B2 Deep sleep wakeup of multi-bank memory 有权
公开(公告)号：US09251869B2
公开(公告)日：2016-02-02
申请号：US14460972
申请日：2014-08-15
申请人： International Business Machines Corporation
发明人： Chad A. Adams , Thinh V. Luong , Jesse D. Smith
IPC分类号： G11C5/14 , G11C11/4074 , G11C8/00 , G06F1/26 , G06F1/32 , G11C8/04 , G11C11/4072 , G11C8/12 , G11C11/4076 , G11C5/06
CPC分类号： G11C5/148 , G06F1/266 , G06F1/3203 , G06F1/3275 , G11C5/063 , G11C5/14 , G11C7/20 , G11C8/04 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076
摘要： A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.

9. 发明申请

US20150380065A1 DEEP SLEEP WAKEUP OF MULTI-BANK MEMORY 有权
标题翻译：多银行休眠唤醒多银行记忆
公开(公告)号：US20150380065A1
公开(公告)日：2015-12-31
申请号：US14460972
申请日：2014-08-15
申请人： International Business Machines Corporation
发明人： Chad A. Adams , Thinh V. Luong , Jesse D. Smith
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G06F1/266 , G06F1/3203 , G06F1/3275 , G11C5/063 , G11C5/14 , G11C7/20 , G11C8/04 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076
摘要： A deep sleep wakeup signal is received at a first memory bank. A first gated memory array supply voltage is increased in response to the receiving the deep sleep wakeup signal at the first memory bank. The first memory array supply voltage is applied to a first memory array. The deep sleep wakeup signal is forwarded to a second memory bank in response to determining the first gated memory array supply voltage has reached a specified voltage.
摘要翻译：深度睡眠唤醒信号在第一存储体处被接收。第一门控存储器阵列电源电压响应于在第一存储体处接收深度睡眠唤醒信号而增加。第一存储器阵列电源电压被施加到第一存储器阵列。响应于确定第一门控存储器阵列电源电压已经达到指定电压，深度睡眠唤醒信号被转发到第二存储器组。

10. 发明授权

US09183906B2 Fine granularity power gating 有权
标题翻译：细粒度电源门控
公开(公告)号：US09183906B2
公开(公告)日：2015-11-10
申请号：US13633217
申请日：2012-10-02
申请人： International Business Machines Corporation
发明人： Chad A. Adams , Harold Pilo
IPC分类号： G11C7/00 , G11C8/10 , G11C8/08 , G11C8/12 , G11C5/14
CPC分类号： G11C8/10 , G11C5/147 , G11C8/08 , G11C8/12
摘要： Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage.
摘要翻译：存储器阵列的行被分割成预定数量的字线组。字线组中的每一行都具有设置在并行电源线之间的字线。字线组中的一行中的每个电源线由字线组中的相邻行共享。字线组的边界上的行具有由相邻字线组的边界上的行共享的电源线。响应于由字线选择的字线组中的一行，字线组中的所有电源线处于全电源电压。相邻字线组中的大多数电源线处于全电源电压。其他字线组中的所有电源线都处于电源门控电压。

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