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1. 发明授权

US10372851B2 Independently projecting a canonical clock 有权
公开(公告)号：US10372851B2
公开(公告)日：2019-08-06
申请号：US15592351
申请日：2017-05-11
申请人： International Business Machines Corporation
发明人： Nathan Buck , Sean M. Carey , Peter C. Elmendorf , Eric A. Foreman , Jeffrey G. Hemmett , Lyle Jackson , Kerim Kalafala , Stephen G. Shuma , Michael H. Wood
IPC分类号： G06F17/50
摘要： A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

2. 发明授权

US09710594B2 Variation-aware timing analysis using waveform construction 有权
公开(公告)号：US09710594B2
公开(公告)日：2017-07-18
申请号：US14936886
申请日：2015-11-10
申请人： International Business Machines Corporation
发明人： Kerim Kalafala , SheshaShayee K. Raghunathan , Debjit Sinha , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5036 , G06F2217/10 , G06F2217/84
摘要： A method of performing variation aware timing analysis for an integrated circuit, a system, and a computer program product are described. The method includes determining one or more voltage waveforms at an output of a first component of the integrated circuit based on respective one or more first processing conditions, and storing waveform information based on the one or more voltage waveforms. The method also includes obtaining an input voltage waveform at an input of a second component of the integrated circuit for a second processing condition based on processing the waveform information, the output of the first component being the input of the second component, and performing the variation aware timing analysis for the second component based on the input voltage waveform.

3. 发明授权

US09495497B1 Dynamic voltage frequency scaling 有权
标题翻译：动态电压频率缩放
公开(公告)号：US09495497B1
公开(公告)日：2016-11-15
申请号：US14960601
申请日：2015-12-07
申请人： International Business Machines Corporation
发明人： Nathan C. Buck , Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/505 , G06F2217/10 , G06F2217/84
摘要： A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.
摘要翻译：用于执行集成电路的动态电压频率缩放的方法，系统和计算机程序产品包括使用规范形式的时钟执行统计时序分析，时钟的规范形式是电压变化的函数。在集成电路的每个测试位置处获得表达定时松弛的规范模型是作为一个或多个可变性源的函数，一个或多个可变性来源之一是电压，并且基于选择执行动态电压 - 频率缩放至少一个时钟周期和使用规范模型的电压。

4. 发明申请

US20160314236A1 Method of Hierarchical Timing Closure Employing Dynamic Load-Sensitive Feedback Constraints 有权
标题翻译：采用动态负载敏感反馈约束的分层时序闭合方法
公开(公告)号：US20160314236A1
公开(公告)日：2016-10-27
申请号：US14691599
申请日：2015-04-21
申请人： International Business Machines Corporation
发明人： Adil Bhanji , Kerim Kalafala , Ravichander Ledalla , Debjit Sinha , Chandramouli Visweswariah , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. The method is applicable for deterministic as well as for statistical timing analyses.
摘要翻译：使用动态负载敏感定时反馈约束来保持所有边界路径的定时精度的集成芯片组件的时序分析通过针对其主要输入和初级输出中的每一个的灵敏度捕获组件内的寄生负载的降序表示来实现到达时间的时间，所需的到达时间到组件父级别的负载表示，作为生成负载敏感反馈约束的一部分。在组件的上下文关闭定时关闭期间，基本负载表示和灵敏度以及更新的负载表示使得能够计算更新的边界约束以进行准确的时序分析。精度提高在定时关闭期间增加了芯片设计人员的生产力，从而缩短了通过定时关闭到制造的芯片设计的时间。该方法适用于确定性以及统计时序分析。

5. 发明授权

US10354046B2 Programmable clock division methodology with in-context frequency checking 有权
公开(公告)号：US10354046B2
公开(公告)日：2019-07-16
申请号：US15810314
申请日：2017-11-13
申请人： International Business Machines Corporation
发明人： Naiju K Abdul , Jennifer E. Basile , Hemlata Gupta , Kerim Kalafala , Jeremy J. Leitzen , Stephen G. Shuma , Manish Verma , James D. Warnock , Michael H. Wood
IPC分类号： G06F17/50
摘要： A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

6. 发明申请

US20160364513A1 VARIABLE ACCURACY PARAMETER MODELING IN STATISTICAL TIMING 有权
标题翻译：统计时间的可变精度参数建模
公开(公告)号：US20160364513A1
公开(公告)日：2016-12-15
申请号：US15235168
申请日：2016-08-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric A. Foreman , Jeffrey G. Hemmett , Kerim Kalafala , Gregory M. Schaeffer , Stephen G. Shuma , Alexander J. Suess , Chandramouli Visweswariah , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F17/5081 , G06F2217/84
摘要： Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.
摘要翻译：系统和方法使用相对较高精度的第一定时计算来计算变量的集成电路设计的平均定时值; 并且使用具有相对较低精度的第二定时计算来计算所述变量的集成电路设计的第一定时值。这样的系统和方法使用第二定时计算来计算用于附加变量集合的集成电路设计的第二定时值; 并计算每个第二定时值与第一定时值的有限差。因此，这些系统和方法基于有限差分来计算第一时间值对附加变量集合的统计灵敏度。此外，这样的系统和方法基于第一定时值对附加值集合的统计灵敏度来计算平均定时值对附加值集合的统计灵敏度。

7. 发明申请

US20160232276A1 METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN EDGE TO AN INBOARD POSITION IN PROCESSING LARGE BLOCK SYNTHESIS (LBS) 有权
公开(公告)号：US20160232276A1
公开(公告)日：2016-08-11
申请号：US14924766
申请日：2015-10-28
申请人： International Business Machines Corporation
发明人： Lukas Daellenbach , Niels Fricke , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072
摘要： A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first and the second timing details.

8. 发明授权

US08984261B2 Store data forwarding with no memory model restrictions 有权
标题翻译：存储数据转发，无内存模式限制
公开(公告)号：US08984261B2
公开(公告)日：2015-03-17
申请号：US14059673
申请日：2013-10-22
申请人： International Business Machines Corporation
发明人： Brian D. Barrick , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Aaron Tsai , Chung-Lung K. Shum , Michael H. Wood
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F13/00 , G06F13/28 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request.
摘要翻译：实施例涉及在流水线微处理器中加载数据。一方面包括发布加载请求，该加载请求包括需要至少一个与高速缓存返回的最大连续粒度数据相同大小的数据块的加载地址。另一方面包括确定加载地址与至少一个块地址匹配。另一方面包括：基于确定存在地址匹配，从缓冲寄存器读取数据块并发送数据以满足加载请求; 在发送数据块之后，将数据块的唯一集合ID与匹配地址的集合ID进行比较; 基于确定存在设置id匹配，继续加载请求，或者基于确定没有设置id匹配，将匹配地址的存储转发状态设置为不存储转发并拒绝加载请求。

9. 发明授权

US08954914B2 Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design 有权
标题翻译：将物理属性分配给用于VLSI芯片设计的高级描述语言的实体的图形方法和产品
公开(公告)号：US08954914B2
公开(公告)日：2015-02-10
申请号：US13855416
申请日：2013-04-02
申请人： International Business Machines Corporation
发明人： John T. Badar , David W. Lewis , Michael H. Wood , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations. After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file. Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations. Physical design attributes can include coordinates and an orientation. The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design.
摘要翻译：在任何物理合成之前，通过将包括位置的物理设计属性分配给电路网表中的可选择的可放置对象的子集来设计集成电路的布局。布局摘要显示在图形用户界面中，以允许设计人员目视检查在其分配位置显示所选对象的布局摘要。在对对象位置进行任何所需的修改之后，位置信息可被格式化为合成输入文件。然后根据分配的位置保持所选对象的固定位置，进行物理合成。物理设计属性可以包括坐标和方位。所选择的可放置对象的子集可以构成集成电路设计的标识数据通路。

10. 发明授权

US08930864B2 Method of sharing and re-using timing models in a chip across multiple voltage domains 有权
标题翻译：在多个电压域中共享和重新使用芯片中的时序模型的方法
公开(公告)号：US08930864B2
公开(公告)日：2015-01-06
申请号：US13633911
申请日：2012-10-03
申请人： International Business Machines Corporation
发明人： Debjit Sinha , Eric J. Fluhr , Stephen G. Shuma , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.
摘要翻译：考虑到制造和环境变化的VLSI电路或芯片设计的时序分析的方法和系统，其中设计包括通过共享和重新使用摘要在多于一个电压域上实例化的门或宏的多个实例。芯片的时序分析包括在抽象生成期间在不同于域的电压域中实例化的宏抽象。定时模型重新用于跨芯片电压域或芯片设计。此外，芯片设计的统计时序分析考虑了其中至少一个定时抽象模型生成时间电压域条件与芯片中的宏实例化域不同的电压域。本发明还提供共享和重新使用统计时序模型或摘要。

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