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1. 发明申请

US20230068471A1 PROXY-BASED INSTRUCTION THROTTLING CONTROL 有权
公开(公告)号：US20230068471A1
公开(公告)日：2023-03-02
申请号：US17460162
申请日：2021-08-28
申请人： International Business Machines Corporation
发明人： Brian Thomas Vanderpool , Gregory Scott Still , Juan Medina , Michael Stephen Floyd , Matthew A. Cooke
IPC分类号： G06F9/50
摘要： Embodiments relate to a system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes establishing a temporal interval that includes a plurality of temporal periods and an interval energy target for one or more processor cores. The method also includes determining for each temporal period a period energy target for the processor cores and determining a processor core throttling state for the processor cores. The method further includes adjusting the respective period energy target and the respective processor core throttling state at the beginning of each successive temporal period. The method also includes converging, subject to the adjusting, as each respective temporal period of the plurality of temporal periods is concluded, a total period energy consumption of the processor cores with the interval energy target.

2. 发明授权

US09811150B2 System and method for controlling idle state exits to manage DI/DT issues 有权
公开(公告)号：US09811150B2
公开(公告)日：2017-11-07
申请号：US14937290
申请日：2015-11-10
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Alan James Drake , Michael Stephen Floyd , Charles Robert Lefurgy , Karthick Rajamani , Tobias Webel
IPC分类号： G06F1/32 , G06F1/26 , G06F9/44
CPC分类号： G06F1/3287 , G06F1/26 , G06F9/4418 , Y02D10/171
摘要： A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.

3. 发明申请

US20150109043A1 ADJUSTABLE DELAY CALIBRATION IN A CRITICAL PATH MONITOR 有权
标题翻译：关键路径监视器中的可调延迟校准
公开(公告)号：US20150109043A1
公开(公告)日：2015-04-23
申请号：US14058428
申请日：2013-10-21
申请人： International Business Machines Corporation
发明人： Alan James Drake , Michael Stephen Floyd , Pawel Owczarczyk , Gregory Scott Still , Marshall Dale Tiner , Xiaobin Yuan
IPC分类号： H03K5/159
CPC分类号： H03K5/159
摘要： A critical path monitor (CPM) having a set of split paths is configured in an integrated circuit (IC) that includes a corresponding set of critical paths. A first and a second split path is configured with a first and a second simulated delay sections and fine delay sections, respectively. A delay of each of the first and second fine delay sections is adjustable in several steps. The delay of the first fine delay section is adjustable differently from the delay of the second fine delay section in response to a common operating condition change. Differently adjusting the delays of the first and the second fine delay sections causes an edge of a pulse to be synchronized between a first edge detector located after the first simulated delay section and a second edge detector located after the second simulated delay section.
摘要翻译：具有一组分离路径的关键路径监视器（CPM）被配置在包括相应的一组关键路径的集成电路（IC）中。第一和第二分割路径分别配置有第一和第二模拟延迟部分和精细延迟部分。第一和第二精细延迟部分中的每一个的延迟可以在几个步骤中调节。响应于共同的操作条件改变，第一精细延迟部分的延迟可以不同于第二精细延迟部分的延迟而不同。不同地调整第一和第二精细延迟部分的延迟导致位于第一模拟延迟部分之后的第一边缘检测器和位于第二模拟延迟部分之后的第二边缘检测器之间的脉冲边缘同步。

4. 发明授权

US11625087B2 Current prediction-based instruction throttling control 有权
公开(公告)号：US11625087B2
公开(公告)日：2023-04-11
申请号：US17460163
申请日：2021-08-28
申请人： International Business Machines Corporation
发明人： Brian Thomas Vanderpool , Gerald Mark Grabowski , Jeffrey A. Stuecheli , Michael Stephen Floyd , Matthew A. Cooke
IPC分类号： G06F1/32 , G06F1/3234 , G06F1/3206
摘要： A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.

5. 发明申请

US20230062546A1 CURRENT PREDICTION-BASED INSTRUCTION THROTTLING CONTROL 有权
公开(公告)号：US20230062546A1
公开(公告)日：2023-03-02
申请号：US17460163
申请日：2021-08-28
申请人： International Business Machines Corporation
发明人： Brian Thomas Vanderpool , Gerald Mark Grabowski , Jeffrey A. Stuecheli , Michael Stephen Floyd , Matthew A. Cooke
IPC分类号： G06F1/3234 , G06F1/3206
摘要： A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes recording an activity level of one or more processor cores within a multicore processing device and translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes determining the one or more charge replenishment requests exceeds a power delivery capacity to the multicore processing device. The method also includes regulating the processing activity of the one or more processor cores to decrease a power consumption for the one or more processing cores.

6. 发明授权

US08941426B1 Extending a clock frequency range of a critical path monitor 有权
标题翻译：延长关键路径监视器的时钟频率范围
公开(公告)号：US08941426B1
公开(公告)日：2015-01-27
申请号：US14093734
申请日：2013-12-02
申请人： International Business Machines Corporation
发明人： Alan James Drake , Michael Stephen Floyd , Pawel Owczarczyk , Gregory Scott Still , Marshall Dale Tiner , Xiaobin Yuan
IPC分类号： H03K3/02 , H03K3/01
CPC分类号： G01R31/31725
摘要： A critical path monitor (CPM) is configured in an integrated circuit (IC). The IC includes a set of critical paths. The CPM includes a set of split paths, a split path in the set of split paths corresponding to a critical path in the set of critical paths, and a split path in the set of split paths including an edge detector. The edge detector is configured with a set of edge detector latches. A set of set-reset (SR) latches is configured such that an edge detector latch is associated with a corresponding SR latch. A reset signal is configured to reach the set of edge detector latches in an offset synchronization with a latch clock signal used in the set of edge detector latches. The CPM is configured to operate using a frequency of the latch clock signal such that the frequency is higher than a threshold frequency.
摘要翻译：关键路径监视器（CPM）在集成电路（IC）中配置。 IC包括一组关键路径。 CPM包括一组分割路径，对应于该组关键路径中的关键路径的分割路径集合中的分割路径，以及包括边缘检测器的分割路径集合中的分割路径。边缘检测器配置有一组边缘检测器锁存器。一组置位（SR）锁存器被配置为使得边沿检测器锁存器与相应的SR锁存器相关联。复位信号被配置为以与边缘检测器锁存器组中使用的锁存时钟信号的偏移同步来到达边缘检测器锁存器组。 CPM被配置为使用锁存时钟信号的频率进行操作，使得频率高于阈值频率。

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