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1. 发明申请

US20200221610A1 MECHANICALLY FLEXIBLE COLD PLATES FOR LOW POWER COMPONENTS 审中-公开
公开(公告)号：US20200221610A1
公开(公告)日：2020-07-09
申请号：US16827645
申请日：2020-03-23
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Mark D. Schultz , Todd E. Takken , Shurong Tian
IPC分类号： H05K7/20 , H01L23/367 , G06F1/20 , H01L23/473
摘要： An assembled circuit board has a topology that defines positions, dimensions and power dissipation of components mounted to the circuit board, including a high power component and one or more low power components. A cold plate makes thermal contact to the high power component through a thermal interface material. A thermally conductive sheet overlays the circuit board and is formed to match the topology of the low power component or components. The sheet has a first portion that makes thermal contact with the cold plate and a second portion that overlays the low power component or components. The cold plate removes heat directly from the high power component and indirectly through the thermally conductive sheet from the low power component or components. The thermally conductive sheet conforms to the topology of the low power components either by preforming or by flexibility.

2. 发明授权

US09880896B2 Error feedback and logging with memory on-chip error checking and correcting (ECC) 有权
公开(公告)号：US09880896B2
公开(公告)日：2018-01-30
申请号：US14320283
申请日：2014-06-30
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule , Vipinchandra Patel
IPC分类号： G06F11/10 , G06F11/07
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048
摘要： Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

3. 发明授权

US09817697B2 Thermal-and spatial-aware task scheduling 有权
公开(公告)号：US09817697B2
公开(公告)日：2017-11-14
申请号：US15080689
申请日：2016-03-25
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Eun Kyung Lee , Yoonho Park
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5094
摘要： A method, apparatus, and computer program product are provided for thermal- and spatial-aware task scheduling. The method may include monitoring a temperature for each core of a central processing unit having a plurality of cores; determining, from the monitoring, a set of hotspot cores from the plurality of cores determining temperature information and distance information for each hotspot core in the set of hotspot cores relative to each of the other cores on the central processing unit; calculating a placement metric for each core of the central processing unit based at least on the determined distance information and the determined temperature information; and scheduling a task by allocating the task to one or more cores of the central processing unit according to the placement metric.

4. 发明授权

US09442512B1 Interface clock frequency switching using a computed insertion delay 有权
标题翻译：接口时钟频率切换使用计算插入延迟
公开(公告)号：US09442512B1
公开(公告)日：2016-09-13
申请号：US14946993
申请日：2015-11-20
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Daniel M. Dreps , Hillery C. Hunter , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： G06F1/00 , G06F1/14
CPC分类号： G06F1/10 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An aspect includes a method of interface clock frequency switching control that includes determining a first clock delay adjustment of a clock signal for an interface at a first clock frequency. A controller determines a second clock delay adjustment for the interface operated at a second clock frequency. The controller computes an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment and frequency and the second clock delay adjustment and frequency. The controller also computes a third clock delay adjustment to operate the interface at a third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency. The clock signal is adjusted based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.
摘要翻译：一个方面包括接口时钟频率切换控制的方法，其包括确定在第一时钟频率下用于接口的时钟信号的第一时钟延迟调整。控制器确定在第二时钟频率下操作的接口的第二时钟延迟调整。控制器基于第一时钟延迟调整和频率以及第二时钟延迟调整和频率来计算时钟信号和接口的数据信号之间的插入延迟。控制器还计算第三时钟延迟调整，以基于插入延迟以及第三时钟频率和第二时钟频率之间的相对差在第三时钟频率操作接口。基于第三时钟延迟调整来调整时钟信号，以将时钟信号的定时与第三时钟频率的数据信号对准。

5. 发明授权

US09374414B2 Embedding global and collective in a torus network with message class map based tree path selection 有权
标题翻译：将全局和集体嵌入到具有基于消息类映射的树路径选择的环网中
公开(公告)号：US09374414B2
公开(公告)日：2016-06-21
申请号：US13975943
申请日：2013-08-26
申请人： International Business Machines Corporation
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
IPC分类号： G06F15/173 , H04L29/08 , G06F11/34 , G06F11/30 , G06F9/30
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
摘要翻译：本发明的实施例提供了一种用于在被组织为环面网络的并行计算机系统中嵌入全局屏障和全局中断网络的方法，系统和计算机程序产品。计算机系统包括多个节点。在一个实施例中，该方法包括从节点的一组接收器中获取输入，将来自接收器的输入划分为多个类，组合每个类的输入以获得结果，并将所述结果发送到一组的节点的发送者。本发明的实施例提供了一种用于将集体网络嵌入组织为环面网络的并行计算机系统中的方法，系统和计算机程序产品。在一个实施例中，该方法包括向环形网络添加集中逻辑以在树结构中的至少一组节点之间路由消息。

6. 发明授权

US09244759B2 Error recovery to enable error-free message transfer between nodes of a computer network 有权
标题翻译：错误恢复，使计算机网络的节点之间无差错的消息传输
公开(公告)号：US09244759B2
公开(公告)日：2016-01-26
申请号：US14148348
申请日：2014-01-06
申请人： International Business Machines Corporation
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd Takken , Burkhard Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16 , G06F11/08 , H03M13/09 , G06F9/46 , G06F11/14 , H04L1/00 , H04L1/16
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.
摘要翻译：一种错误恢复方法，可在计算机网络的节点之间实现无错误的消息传输。网络的第一节点通过节点之间的链路将分组发送到网络的第二节点，并且第一节点在链路的发送端保持分组的副本，直到第一节点从第二节点接收到确认该数据包被收到没有错误。第二个节点测试数据包以确定数据包是否无错误。如果数据包不是无错误的，则第二个节点设置一个标志，以将数据包标记为已损坏。第二个节点向第一个节点返回确认，指定该数据包是否被接收到有或没有错误。当分组被接收到错误时，链路返回到已知状态，并且分组被再次发送到第二节点。

7. 发明申请

US20150236004A1 IMPLEMENTING INVERTED MASTER-SLAVE 3D SEMICONDUCTOR STACK 审中-公开
标题翻译：实施逆向主从3D三维半导体堆栈
公开(公告)号：US20150236004A1
公开(公告)日：2015-08-20
申请号：US14699988
申请日：2015-04-29
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Shawn A. Hall , Todd E. Takken
IPC分类号： H01L25/00 , H01L23/00 , H01L27/108
CPC分类号： H01L25/18 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/50 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/10844 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1431 , H01L2924/1436 , H01L2924/15151 , H01L2924/15313 , H01L2924/19041 , H01L2924/19105
摘要： A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
摘要翻译：提供了一种用于实现增强的三维（3D）半导体堆叠的方法和装置。芯片载体具有第一长度和第一宽度的孔。第一芯片具有大于第一长度的第二长度或大于第一宽度的第二宽度中的至少一个; 第二芯片附接到第一芯片，第二芯片具有小于第一长度的第三长度或小于第一宽度的第三宽度中的至少一个; 所述第一芯片通过由所述第一和第二长度或所述第一和第二宽度中的至少一个限定的重叠区域中的连接连接到所述芯片载体; 第二芯片延伸到孔中; 以及散热器，其附接到所述芯片载体并与所述第一芯片热接触以散热来自所述第一芯片和所述第二芯片的热量。

8. 发明申请

US20150212886A1 ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC) 有权
标题翻译：错误反馈和记录与内存片上错误检查和更正（ECC）
公开(公告)号：US20150212886A1
公开(公告)日：2015-07-30
申请号：US14320283
申请日：2014-06-30
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Hillery C. Hunter , Charles Arthur Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule , Vipinchandra Patel
IPC分类号： G06F11/10
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048
摘要： Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
摘要翻译：可以在片上存储器中执行错误检查和校正（ECC），其中错误由控制器而不是片上存储器校正。可以标记控制器以示出已经发生错误以及其在存储器中发生的位置。控制器可以访问与错误相关联的ECC位，并可能修复不正确的数据。可以与存储器的读取操作并行地进行错误检查，以便降低延迟。

9. 发明申请

US20150212885A1 ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC) 有权
公开(公告)号：US20150212885A1
公开(公告)日：2015-07-30
申请号：US14168460
申请日：2014-01-30
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule , Vipinchandra Patel
IPC分类号： G06F11/10 , G06F11/07
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048
摘要： Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

10. 发明授权

US08927336B2 Packaging structure 有权
标题翻译：包装结构
公开(公告)号：US08927336B2
公开(公告)日：2015-01-06
申请号：US13968099
申请日：2013-08-15
申请人： International Business Machines Corporation
发明人： Evan G. Colgan , Paul W. Coteus , Robert L. Wisnieff
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/00 , H01L23/538
CPC分类号： H01L23/5386 , H01L23/473 , H01L23/5384 , H01L23/5385 , H01L24/00 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2924/1434 , H01L2924/15311 , H01L2924/3511 , H01L2924/37001 , H01L2924/014
摘要： A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.
摘要翻译：提供了组装封装结构的方法，并且包括以面对面的布置直接电互连第一和第二芯片的相应有效表面，将第一和第二芯片的相应侧壁中的至少一个电气互连到公共芯片并且使相对于公共芯片横向地定向第一和第二芯片的各自的有源表面。

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