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1. 发明申请

US20110296138A1 FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS 有权
标题翻译：处理器之间的快速远程通信和计算
公开(公告)号：US20110296138A1
公开(公告)日：2011-12-01
申请号：US12789082
申请日：2010-05-27
申请人： JOHN BRUCE CARTER , ELMOOTAZBELLAH NABIL ELNOZAHY , AHMED GHEITH , ERIC VAN HANSBERGEN , KARTHICK RAJAMANI , WILLIAM EVAN SPEIGHT , LIXIN ZHANG
发明人： JOHN BRUCE CARTER , ELMOOTAZBELLAH NABIL ELNOZAHY , AHMED GHEITH , ERIC VAN HANSBERGEN , KARTHICK RAJAMANI , WILLIAM EVAN SPEIGHT , LIXIN ZHANG
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/544
摘要： A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译：在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法，系统和计算机可用程序产品。核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。

2. 发明申请

US20090198962A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE INCLUDING ADDRESS TYPE TAG BIT 有权
标题翻译：数据处理系统，具有分支目标地址高速缓存的数据处理的处理器和方法，包括地址类型标记位
公开(公告)号：US20090198962A1
公开(公告)日：2009-08-06
申请号：US12024203
申请日：2008-02-01
申请人： DAVID S. LEVITAN , LIXIN ZHANG
发明人： DAVID S. LEVITAN , LIXIN ZHANG
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/30174 , G06F9/3802 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3889
摘要： In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括执行单元和指令排序逻辑，其从存储器系统中取出指令以供执行单元执行。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址预测电路，同时保持提供用于第一分支目标地址预测的存储的第一条目，其中第一分支目标地址预测将第一指令获取地址与要用作指令获取地址的第一分支目标地址相关联，用于将第一指令提取地址与不同的第二分支目标地址相关联的第二分支目标地址预测。第一条目指示第一指令获取地址的第一指令地址类型，第二条目指示第一指令提取地址的第二指令地址类型。

3. 发明申请

US20090198981A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE STORING DIRECT PREDICTIONS 失效
标题翻译：数据处理系统，具有分支目标地址的数据处理的处理器和方法高速缓存存储直接预测
公开(公告)号：US20090198981A1
公开(公告)日：2009-08-06
申请号：US12024197
申请日：2008-02-01
申请人： DAVID S. LEVITAN , LIXIN ZHANG
发明人： DAVID S. LEVITAN , LIXIN ZHANG
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元和指令排序逻辑，其提取由执行单元执行的指令。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址高速缓存（BTAC），其具有至少一个直接条目，为直接分支目标地址预测提供存储，该直接分支目标地址预测将第一指令获取地址与分支目标地址相关联，以将分配目标地址用作紧接在该目标地址之后的第二指令获取地址第一指令获取地址和至少一个间接条目提供用于间接分支目标地址预测的存储，用于将第三指令获取地址与分支目标地址相关联，以将分配目标地址用作在第三指令提取地址和中间地址之后的第四指令获取地址第五指令提取地址。

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