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1. 发明授权

US09130056B1 Bi-layer wafer-level underfill mask for wafer dicing and approaches for performing wafer dicing 有权
标题翻译：用于晶片切割的双层晶片级底部填充掩模和用于执行晶片切割的方法
公开(公告)号：US09130056B1
公开(公告)日：2015-09-08
申请号：US14506455
申请日：2014-10-03
申请人： James M. Holden , James S. Papanu , Wei-Sheng Lei , Brad Eaton , Ajay Kumar
发明人： James M. Holden , James S. Papanu , Wei-Sheng Lei , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/78 , H01L21/46 , H01L21/301 , H01L21/82 , H01L21/56 , H01L21/3065
CPC分类号： H01L21/3065 , H01L21/3081 , H01L21/561 , H01L21/563 , H01L21/78 , H01L2224/16145 , H01L2224/16225
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves laminating a pre-patterned bi-layer wafer-level underfill material stack on the integrated circuits of the semiconductor wafer. The pre-patterned bi-layer wafer-level underfill material stack has regions corresponding to the integrated circuits and gaps corresponding to dicing streets between the integrated circuits. The method also involves plasma etching to form trenches in the semiconductor wafer in alignment with the dicing streets to singulate the integrated circuits. An upper layer of the pre-patterned bi-layer wafer-level underfill material stack protects the integrated circuits during the plasma etching.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个示例中，在其前侧上划分具有集成电路的半导体晶片的方法包括在半导体晶片的集成电路上层叠预先构图的双层晶片级底层填充材料堆叠。预图案化双层晶片级底层填充材料堆叠具有对应于集成电路和对应于集成电路之间的切割街道的间隙的区域。该方法还包括等离子体蚀刻以在半导体晶片中形成与切割街道对准的沟槽，以对集成电路进行分割。预先图案化的双层晶片级底部填充材料堆叠的上层在等离子体蚀刻期间保护集成电路。

2. 发明授权

US09281244B1 Hybrid wafer dicing approach using an adaptive optics-controlled laser scribing process and plasma etch process 有权
标题翻译：使用自适应光学控制激光划线工艺和等离子体蚀刻工艺的混合晶片切割方法
公开(公告)号：US09281244B1
公开(公告)日：2016-03-08
申请号：US14490598
申请日：2014-09-18
申请人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
发明人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/02 , H01L21/78 , H01L21/308 , H01L21/3065 , H01L21/67 , H01J37/32 , B23K26/36
CPC分类号： H01L21/78 , B23K26/364 , H01J37/32889 , H01J2237/335 , H01L21/3065 , H01L21/3086 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。然后用自适应光学控制激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

3. 发明授权

US09209084B2 Maskless hybrid laser scribing and plasma etching wafer dicing process 有权
公开(公告)号：US09209084B2
公开(公告)日：2015-12-08
申请号：US14454656
申请日：2014-08-07
申请人： Wei-Sheng Lei , Brad Eaton , James S. Papanu , Ajay Kumar
发明人： Wei-Sheng Lei , Brad Eaton , James S. Papanu , Ajay Kumar
IPC分类号： H01L21/00 , H01L21/78 , H01L21/3065 , H01L21/82 , B23K26/00 , B23K26/06
CPC分类号： H01L21/78 , B23K26/0006 , B23K26/0624 , B23K26/50 , B23K26/53 , B23K26/57 , B23K2101/40 , B23K2103/56 , H01L21/3065 , H01L21/82
摘要： Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

4. 发明授权

US09177861B1 Hybrid wafer dicing approach using laser scribing process based on an elliptical laser beam profile or a spatio-temporal controlled laser beam profile 有权
标题翻译：使用基于椭圆激光束轮廓或时空控制激光束轮廓的激光划线工艺的混合晶片切割方法
公开(公告)号：US09177861B1
公开(公告)日：2015-11-03
申请号：US14491728
申请日：2014-09-19
申请人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
发明人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/00 , H01L21/78 , H01L21/308 , H01L21/3065 , H01L21/67 , H01J37/32 , B23K26/36 , B23K26/16
CPC分类号： H01L21/3065 , B23K26/0736 , B23K26/367 , B23K26/38 , B23K2103/56 , H01J37/32 , H01J37/32889 , H01J2237/334 , H01J2237/335 , H01L21/02057 , H01L21/30655 , H01L21/3081 , H01L21/3086 , H01L21/67069 , H01L21/67092 , H01L21/78
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an elliptical or a spatio-temporal controlled laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。然后用椭圆形或空间 - 时间控制的激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

5. 发明申请

US20150279739A1 DICING PROCESSES FOR THIN WAFERS WITH BUMPS ON WAFER BACKSIDE 有权
标题翻译：用于在背面放置波纹的薄膜的定位方法
公开(公告)号：US20150279739A1
公开(公告)日：2015-10-01
申请号：US14226038
申请日：2014-03-26
申请人： Wei-Sheng Lei , James S. Papanu , Aparna Iyer , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , James S. Papanu , Aparna Iyer , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/78 , H01L23/544
CPC分类号： H01L21/78 , H01L21/3065 , H01L21/6835 , H01L21/6836 , H01L23/544 , H01L2221/68327 , H01L2221/6834 , H01L2223/54426 , H01L2223/5446 , H01L2224/11 , H01L2224/16145 , H01L2224/16225
摘要： Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.
摘要翻译：描述了用于前侧激光划片加背面凸块形成和激光划线和等离子体蚀刻切割工艺的方法。例如，在前侧具有集成电路的半导体晶片的切割方法包括在第一激光划线工序之间，在集成电路之间的正面侧形成第一划线。该方法还涉及在半导体晶片的背面形成金属凸块阵列，每个阵列对应于一个集成电路。该方法还涉及在金属凸块阵列之间的背侧，第二激光划线工艺之间形成第二刻划线，其中第二刻划线与第一划刻线对准。该方法还包括通过第二划线等离子体蚀刻半导体晶片以对集成电路进行分离。

6. 发明申请

US20150214109A1 WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH WITH MASK PLASMA TREATMENT FOR IMPROVED MASK ETCH RESISTANCE 有权
标题翻译：使用混合激光切割和等离子体蚀刻方法进行抛光加工，具有改进的掩模抗蚀性的掩模等离子体处理
公开(公告)号：US20150214109A1
公开(公告)日：2015-07-30
申请号：US14167300
申请日：2014-01-29
申请人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar , James S. Papanu , Jungrae Park
发明人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar , James S. Papanu , Jungrae Park
IPC分类号： H01L21/78 , H01J37/32 , H01L21/67 , H01L21/308 , H01L21/3065
CPC分类号： H01L21/78 , B23K26/361 , B23K2103/172 , B23K2103/50 , H01L21/0273 , H01L21/3065 , H01L21/30655 , H01L21/3081 , H01L21/3086 , H01L21/31058 , H01L21/31127 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。将掩模暴露于等离子体处理工艺以增加掩模的耐蚀刻性。用激光划线工艺对掩模进行图案化，以在掩模中提供间隙，使间隙暴露集成电路之间的半导体晶片的区域。在将掩模暴露于等离子体处理工艺之后，通过掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

7. 发明授权

US09076860B1 Residue removal from singulated die sidewall 有权
标题翻译：从单个模具侧壁残留除去
公开(公告)号：US09076860B1
公开(公告)日：2015-07-07
申请号：US14248165
申请日：2014-04-08
申请人： Wei-Sheng Lei , Prabhat Kumar , James S. Papanu , Ajay Kumar , Brad Eaton
发明人： Wei-Sheng Lei , Prabhat Kumar , James S. Papanu , Ajay Kumar , Brad Eaton
IPC分类号： H01L21/78 , H01L21/3065 , H01L21/308 , H01L21/67
CPC分类号： H01L21/02076 , H01L21/67092 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。该方法还包括用激光划线工艺对掩模进行图案化以在掩模中提供间隙，在半导体晶片的间隙暴露集成电路之间的半导体晶片。该方法还包括通过掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。该方法还涉及在等离子体蚀刻半导体晶片之后，从单个集成电路的侧壁去除蚀刻残留物。

8. 发明申请

US20160315009A1 UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH 有权
标题翻译：使用混合激光扫描和等离子体蚀刻方法进行波长涂覆的载体膜的UV固化预处理
公开(公告)号：US20160315009A1
公开(公告)日：2016-10-27
申请号：US14697391
申请日：2015-04-27
申请人： Wei-Sheng Lei , Brad Eaton , Jungrae Park , Ajay Kumar , James S. Papanu , Prabhat Kumar
发明人： Wei-Sheng Lei , Brad Eaton , Jungrae Park , Ajay Kumar , James S. Papanu , Prabhat Kumar
IPC分类号： H01L21/78 , H01L21/683 , H01L21/268 , H01L21/67 , H01L21/308 , H01L21/3065
CPC分类号： H01L21/78 , H01L21/268 , H01L21/3065 , H01L21/3086 , H01L21/67069 , H01L21/67207 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个示例中，在半导体晶片的正面上切割具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附在基板载体的切割带上。在将半导体晶片粘附在切割带上之后，用UV固化工艺处理切割带。在通过UV固化处理处理切割带之后，在半导体晶片的前侧形成切割掩模，该切割掩模覆盖并保护集成电路。用激光刻划工艺对切割掩模进行图案化，以在切割掩模之间提供间隙，在半导体晶片的间隙暴露在集成电路之间。通过切割掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

9. 发明授权

US09196536B1 Hybrid wafer dicing approach using a phase modulated laser beam profile laser scribing process and plasma etch process 有权
标题翻译：使用相位调制激光束轮廓激光划线工艺和等离子体蚀刻工艺的混合晶片切割方法
公开(公告)号：US09196536B1
公开(公告)日：2015-11-24
申请号：US14497027
申请日：2014-09-25
申请人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
发明人： Jungrae Park , Wei-Sheng Lei , James S. Papanu , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/82 , H01L21/78 , H01L21/3065 , H01L21/67 , H01J37/32 , B23K26/40 , B23K26/36
CPC分类号： H01L21/3065 , H01J37/32 , H01J37/32889 , H01J37/32899 , H01J37/32926 , H01J2237/2487 , H01J2237/334 , H01J2237/3341 , H01J2237/335 , H01L21/02057 , H01L21/30655 , H01L21/3081 , H01L21/67069 , H01L21/67092 , H01L21/67115 , H01L21/78
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a phase modulated laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。然后用相位调制的激光束轮廓激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

10. 发明授权

US09159624B1 Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach 有权
标题翻译：使用混合激光划线和等离子体蚀刻方法对用于晶片切割的聚合物干膜进行真空层压
公开(公告)号：US09159624B1
公开(公告)日：2015-10-13
申请号：US14589913
申请日：2015-01-05
申请人： Wei-Sheng Lei , Prabhat Kumar , James S. Papanu , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Prabhat Kumar , James S. Papanu , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/78 , H01L21/8234
CPC分类号： H01L21/78 , H01L21/6836 , H01L21/8234 , H01L2221/68327 , H01L2221/6834
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括通过干膜真空层压将聚合物掩模层层压到半导体晶片的正面上，该聚合物掩模层覆盖并保护集成电路。该方法还包括用激光划线工艺图案化聚合物掩模层，以在聚合物掩模层中提供间隙，间隙暴露集成电路之间的半导体晶片的区域。该方法还包括通过聚合物掩模层中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。该方法还涉及在等离子体蚀刻半导体晶片之后，去除聚合物掩模层。

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