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1. 发明申请

US20120187527A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR 有权
标题翻译：形成半导体器件终止及其结构的方法
公开(公告)号：US20120187527A1
公开(公告)日：2012-07-26
申请号：US13227011
申请日：2011-09-07
申请人： Jaume Roig Guitart , Peter Moens , Zia Hossain
发明人： Jaume Roig Guitart , Peter Moens , Zia Hossain
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0688 , H01L29/0692 , H01L29/402 , H01L29/7395 , H01L29/74 , H01L29/872
摘要： At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
摘要翻译：至少一个实施例涉及半导体边缘终端结构，其中边缘终端结构包括多个掺杂层和缓冲层。

2. 发明授权

US09490372B2 Method of forming a semiconductor device termination and structure therefor 有权
标题翻译：形成半导体器件端接的方法及其结构
公开(公告)号：US09490372B2
公开(公告)日：2016-11-08
申请号：US13227011
申请日：2011-09-07
申请人： Jaume Roig Guitart , Peter Moens , Zia Hossain
发明人： Jaume Roig Guitart , Peter Moens , Zia Hossain
IPC分类号： H01L29/06 , H01L29/872 , H01L21/761 , H01L29/40 , H01L29/739 , H01L29/74
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0688 , H01L29/0692 , H01L29/402 , H01L29/7395 , H01L29/74 , H01L29/872
摘要： At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
摘要翻译：至少一个实施例涉及半导体边缘终端结构，其中边缘终端结构包括多个掺杂层和缓冲层。

3. 发明申请

US20120187526A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR 审中-公开
标题翻译：形成半导体器件终止及其结构的方法
公开(公告)号：US20120187526A1
公开(公告)日：2012-07-26
申请号：US13011590
申请日：2011-01-21
申请人： Jaume Roig-Guitart , Zia Hossain , Peter Moens
发明人： Jaume Roig-Guitart , Zia Hossain , Peter Moens
IPC分类号： H01L23/58 , H01L21/761
CPC分类号： H01L21/761 , H01L2924/0002 , H01L2924/00
摘要： At least one exemplary embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several conductivity layers and a buffer layer.
摘要翻译：至少一个示例性实施例涉及半导体边缘终端结构，其中边缘终端结构包括若干导电层和缓冲层。

4. 发明申请

US20100140698A1 ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME 有权
标题翻译：电子设备，其中包括一个TRENCH和一个导电结构及其形成过程
公开(公告)号：US20100140698A1
公开(公告)日：2010-06-10
申请号：US12331985
申请日：2008-12-10
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

5. 发明申请

US20110156141A1 TRANSISTOR AND METHOD THEREOF 有权
标题翻译：晶体管及其方法
公开(公告)号：US20110156141A1
公开(公告)日：2011-06-30
申请号：US12651118
申请日：2009-12-31
申请人： Jaume Roig-Guitart , Peter Moens
发明人： Jaume Roig-Guitart , Peter Moens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/66659
摘要： An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.
摘要翻译：电子设备可以包括第一导电类型的第一阱区域和第二导电类型的第二阱区域并邻接第一阱区域。第一导电类型和第二导电类型可以是相反的导电类型。在一个实施例中，绝缘体区域可以延伸到第一阱区域中，其中绝缘体区域和第一阱区域邻接并限定界面，并且从顶视图，绝缘体区域可以包括朝向第一界面延伸的第一特征并且绝缘体区域可以限定由第一特征界定的第一空间，其中来自最接近第一界面的第一特征的一部分的尺寸至少为零。栅极结构可以覆盖在第一和第二阱区域之间的界面。

6. 发明授权

US08299528B2 Transistor and method thereof 有权
标题翻译：晶体管及其方法
公开(公告)号：US08299528B2
公开(公告)日：2012-10-30
申请号：US12651118
申请日：2009-12-31
申请人： Jaume Roig-Guitart , Peter Moens
发明人： Jaume Roig-Guitart , Peter Moens
IPC分类号： H01L29/08 , H01L29/165 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/66659
摘要： An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.
摘要翻译：电子设备可以包括第一导电类型的第一阱区域和第二导电类型的第二阱区域并邻接第一阱区域。第一导电类型和第二导电类型可以是相反的导电类型。在一个实施例中，绝缘体区域可以延伸到第一阱区域中，其中绝缘体区域和第一阱区域邻接并限定界面，并且从顶视图，绝缘体区域可以包括朝向第一界面延伸的第一特征并且绝缘体区域可以限定由第一特征界定的第一空间，其中来自最接近第一界面的第一特征的一部分的尺寸至少为零。栅极结构可以覆盖在第一和第二阱区域之间的界面。

7. 发明授权

US08298889B2 Process of forming an electronic device including a trench and a conductive structure therein 有权
标题翻译：在其中形成包括沟槽和导电结构的电子器件的工艺
公开(公告)号：US08298889B2
公开(公告)日：2012-10-30
申请号：US12331985
申请日：2008-12-10
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L21/00
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

8. 发明授权

US08648398B2 Electronic device and a transistor including a trench and a sidewall doped region 有权
标题翻译：电子器件和包括沟槽和侧壁掺杂区域的晶体管
公开(公告)号：US08648398B2
公开(公告)日：2014-02-11
申请号：US13627287
申请日：2012-09-26
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

9. 发明申请

US20140103421A1 SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140103421A1
公开(公告)日：2014-04-17
申请号：US13654143
申请日：2012-10-17
申请人： Zia Hossain , Juraj Vavro , Peter Moens
发明人： Zia Hossain , Juraj Vavro , Peter Moens
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0688 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66712 , H01L29/7395 , H01L29/7811
摘要： In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination.
摘要翻译：在一个实施例中，半导体器件涉及使用一个或多个超结沟槽进行端接。

10. 发明授权

US07723800B2 Deep trench isolation for power semiconductors 有权
标题翻译：功率半导体的深沟槽隔离
公开(公告)号：US07723800B2
公开(公告)日：2010-05-25
申请号：US12126803
申请日：2008-05-23
申请人： Peter Moens , Bart Desoete
发明人： Peter Moens , Bart Desoete
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/0661
摘要： An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.
摘要翻译：集成功率半导体器件具有隔离结构，该隔离结构具有两个或更多个隔离沟槽，以及隔离沟槽之间的一个或多个区域，以及耦合到该区域的偏置布置，以分隔隔离沟槽之间的隔离结构的电压。通过划分电压，可以提高给定的器件面积或器件的给定复杂度等反压击穿电压特性，例如电压电平，可靠性和稳定性，并且可以减少或避免隔离结构中的弱点处的雪崩击穿。

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