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1. 发明申请

US20100140698A1 ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME 有权
标题翻译：电子设备，其中包括一个TRENCH和一个导电结构及其形成过程
公开(公告)号：US20100140698A1
公开(公告)日：2010-06-10
申请号：US12331985
申请日：2008-12-10
申请人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
发明人： Jaume Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

2. 发明授权

US07723800B2 Deep trench isolation for power semiconductors 有权
标题翻译：功率半导体的深沟槽隔离
公开(公告)号：US07723800B2
公开(公告)日：2010-05-25
申请号：US12126803
申请日：2008-05-23
申请人： Peter Moens , Bart Desoete
发明人： Peter Moens , Bart Desoete
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/0661
摘要： An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.
摘要翻译：集成功率半导体器件具有隔离结构，该隔离结构具有两个或更多个隔离沟槽，以及隔离沟槽之间的一个或多个区域，以及耦合到该区域的偏置布置，以分隔隔离沟槽之间的隔离结构的电压。通过划分电压，可以提高给定的器件面积或器件的给定复杂度等反压击穿电压特性，例如电压电平，可靠性和稳定性，并且可以减少或避免隔离结构中的弱点处的雪崩击穿。

3. 发明申请

US20110156141A1 TRANSISTOR AND METHOD THEREOF 有权
标题翻译：晶体管及其方法
公开(公告)号：US20110156141A1
公开(公告)日：2011-06-30
申请号：US12651118
申请日：2009-12-31
申请人： Jaume Roig-Guitart , Peter Moens
发明人： Jaume Roig-Guitart , Peter Moens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/66659
摘要： An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.
摘要翻译：电子设备可以包括第一导电类型的第一阱区域和第二导电类型的第二阱区域并邻接第一阱区域。第一导电类型和第二导电类型可以是相反的导电类型。在一个实施例中，绝缘体区域可以延伸到第一阱区域中，其中绝缘体区域和第一阱区域邻接并限定界面，并且从顶视图，绝缘体区域可以包括朝向第一界面延伸的第一特征并且绝缘体区域可以限定由第一特征界定的第一空间，其中来自最接近第一界面的第一特征的一部分的尺寸至少为零。栅极结构可以覆盖在第一和第二阱区域之间的界面。

4. 发明申请

US20100105188A1 DOUBLE TRENCH FOR ISOLATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：用于隔离半导体器件的双光栅
公开(公告)号：US20100105188A1
公开(公告)日：2010-04-29
申请号：US12651683
申请日：2010-01-04
申请人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter MOENS , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/762
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及在第二深沟槽中的第二绝缘体（130），并且延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它桶隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

5. 发明授权

US07667270B2 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US07667270B2
公开(公告)日：2010-02-23
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/331
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

6. 发明申请

US20060244029A1 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US20060244029A1
公开(公告)日：2006-11-02
申请号：US11399377
申请日：2006-04-07
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119 , H01L21/76
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及第二深沟槽中的第二绝缘体（130），并延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它部分隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

7. 发明申请

US20130020637A1 ELECTRONIC DEVICE AND A TRANSISTOR INCLUDING A TRENCH AND A SIDEWALL DOPED REGION 有权
标题翻译：电子设备和包括TRENCH和SIDEWALL DOPED区域的晶体管
公开(公告)号：US20130020637A1
公开(公告)日：2013-01-24
申请号：US13627287
申请日：2012-09-26
申请人： Juame Roig-Guitart , Peter Moens , Marnix Tack
发明人： Juame Roig-Guitart , Peter Moens , Marnix Tack
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/456 , H01L29/66719 , H01L29/7809
摘要： An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
摘要翻译：电子器件可以包括具有主表面的第一层，与主表面相邻的阱区，以及与主表面和阱区间隔开的掩埋掺杂区。电子器件还可以包括朝向掩埋掺杂区域延伸的沟槽，其中沟槽具有侧壁，以及沿沟槽侧壁的侧壁掺杂区域，其中侧壁掺杂区域延伸到比阱区深的深度。第一层和埋藏区具有第一导电类型，并且阱区具有与第一导电类型相反的第二导电类型。电子器件可以在沟槽内包括导电结构，其中导电结构电连接到掩埋掺杂区并与侧壁掺杂区电绝缘。还描述了用于形成电子设备的过程。

8. 发明申请

US20120187527A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE TERMINATION AND STRUCTURE THEREFOR 有权
标题翻译：形成半导体器件终止及其结构的方法
公开(公告)号：US20120187527A1
公开(公告)日：2012-07-26
申请号：US13227011
申请日：2011-09-07
申请人： Jaume Roig Guitart , Peter Moens , Zia Hossain
发明人： Jaume Roig Guitart , Peter Moens , Zia Hossain
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0688 , H01L29/0692 , H01L29/402 , H01L29/7395 , H01L29/74 , H01L29/872
摘要： At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
摘要翻译：至少一个实施例涉及半导体边缘终端结构，其中边缘终端结构包括多个掺杂层和缓冲层。

9. 发明授权

US07915155B2 Double trench for isolation of semiconductor devices 有权
标题翻译：用于隔离半导体器件的双沟槽
公开(公告)号：US07915155B2
公开(公告)日：2011-03-29
申请号：US12651683
申请日：2010-01-04
申请人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
发明人： Peter Moens , Marnix Tack , Sylvie Boonen , Paul Colson
IPC分类号： H01L21/22
CPC分类号： H01L21/3081 , H01L21/3083 , H01L21/76205 , H01L21/76229
摘要： Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.
摘要翻译：半导体器件具有衬底（50），掩埋层（55），从表面接触延伸到掩埋层的有源区，在朝向掩埋层延伸的第一沟槽中的绝缘体（130），以隔离有源区，以及在第二深沟槽中的第二绝缘体（130），并且延伸穿过所述掩埋层以将所述掩埋层和所述有源区域与所述衬底的其它桶隔离。该双沟槽可以帮助减少有源器件与其他器件之间的电气隔离所需的面积。这样的面积减少可以实现多单元超MOS器件中的更大的集成或更多的单元，并且因此改进诸如Ron的性能参数。可以使用第一掩模制造双沟槽以同时蚀刻两个沟槽，并且随后使用第二掩模来更深地蚀刻第二深沟槽。

10. 发明申请

US20090014785A1 SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN PROPERTIES AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有改进的破坏特性的半导体器件及其制造方法
公开(公告)号：US20090014785A1
公开(公告)日：2009-01-15
申请号：US11828973
申请日：2007-07-26
申请人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
发明人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7809
摘要： The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
摘要翻译：本发明提供一种半导体器件（20），其包括形成在由层（1,2,3）的叠层（4）形成的半导体衬底中的沟槽（5），第一生长电介质材料的层（6）覆盖所述沟槽（5）的侧壁和底部，所述层（6）在所述沟槽（5）的底部包括一个或多个凹口（13）以及一个或多个由第二沉积介电材料形成的间隔物（14）填充由第一种生长的电介质材料形成的层（6）中的一个或多个凹口（13）。根据本发明的半导体器件（20）显示出改进的击穿电压和导通电阻。本发明还提供了制造这种半导体器件（20）的方法。

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