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1. 发明授权

US07941777B1 Generating a module interface for partial reconfiguration design flows 有权
标题翻译：生成部分重新配置设计流程的模块接口
公开(公告)号：US07941777B1
公开(公告)日：2011-05-10
申请号：US11891141
申请日：2007-08-08
申请人： Jay T. Young , W. Story Leavesley, III
发明人： Jay T. Young , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of processing a logical netlist for implementing a circuit design within a programmable logic device includes identifying a dynamically reconfigurable module (DRM) including at least one port from the logical netlist and determining whether the port connects with function logic for a function of the DRM. If the port connects with function logic, logic is inferred that connects the function logic with logic that is external to the DRM. If the port does not connect with function logic, logic is inferred that connects the port of the DRM with logic that is external to the DRM according to an attribute associated with the port. The logical netlist is updated to specify the inferred logic.
摘要翻译：一种处理用于在可编程逻辑设备内实现电路设计的逻辑网表的方法包括：从逻辑网表中识别包括至少一个端口的动态可重配置模块（DRM），并确定该端口是否与用于DRM功能的功能逻辑连接。如果端口与功能逻辑连接，则推断逻辑将功能逻辑与DRM外部的逻辑连接起来。如果端口不与功能逻辑连接，则推断逻辑根据与端口相关联的属性将DRM的端口与DRM外部的逻辑连接。更新逻辑网表以指定推断的逻辑。

2. 发明授权

US08332788B1 Generating a module interface for partial reconfiguration design flows 有权
标题翻译：生成部分重新配置设计流程的模块接口
公开(公告)号：US08332788B1
公开(公告)日：2012-12-11
申请号：US13077544
申请日：2011-03-31
申请人： Jay T. Young , W. Story Leavesley, III
发明人： Jay T. Young , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.
摘要翻译：一种处理用于实现可编程集成电路内的电路设计的逻辑网表的方法包括从逻辑网表识别包括端口的动态可重配置模块（DRM）。 DRM定义了与不能通过端口动态重新配置的模块进行通信的集成电路的动态可重配置区域。 DRM的第一电路和DRM外部的电路被实现。第一个电路通过端口连接到DRM外部的电路。 DRM外部的电路在不可动态重新配置的模块内。该方法还包括将连接DRM外部的电路的路由资源锁定到与端口的DRM的边界相关联的位置; 并通过重新使用锁定的路由资源来实现DRM的第二电路。路由第二电路以连接到与端口的DRM边界相关联的位置。

3. 发明授权

US07490312B1 Partition-based incremental implementation flow for use with a programmable logic device 有权
标题翻译：用于可编程逻辑器件的基于分区的增量实现流程
公开(公告)号：US07490312B1
公开(公告)日：2009-02-10
申请号：US11501156
申请日：2006-08-08
申请人： Emil S. Ochotta , William W. Stiehl , Eric Shiflet , W. Story Leavesley, III
发明人： Emil S. Ochotta , William W. Stiehl , Eric Shiflet , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.
摘要翻译：用于可编程逻辑器件的增量流的方法可以包括识别电路设计的硬件描述语言表示的元件并且为所选择的元件指定分区的层级。来自电路设计的先前实现流程的部分实现数据可以与相应的分区相关联。可以在电路设计的增量流程期间重新使用来自至少一个分区的先前实现流程的实现数据的选定部分。

4. 发明授权

US07620927B1 Method and apparatus for circuit design closure using partitions 有权
标题翻译：使用分区的电路设计闭合的方法和装置
公开(公告)号：US07620927B1
公开(公告)日：2009-11-17
申请号：US11639618
申请日：2006-12-15
申请人： Emil S. Ochotta , William W. Stiehl , Eric M. Shiflet , W. Story Leavesley, III
发明人： Emil S. Ochotta , William W. Stiehl , Eric M. Shiflet , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.
摘要翻译：实现电路设计的方法可以包括选择要实现的电路设计，其中电路设计包括多个分区，以及接收指定分区属性的值的用户输入。分区属性可以与电路设计的多个分区中的所选择的一个相关联。该方法还可以包括在电路设计上执行增量实现流程，以便至少部分地根据分区属性的值选择性地修改所选择的分区的先前实现的部分。

5. 发明授权

US07392498B1 Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device 有权
标题翻译：用于实现可编程逻辑器件的预先实现的电路设计的方法和装置
公开(公告)号：US07392498B1
公开(公告)日：2008-06-24
申请号：US10993887
申请日：2004-11-19
申请人： Sankaranarayanan Srinivasan , W. Story Leavesley, III , George L. McHugh , Douglas P. Wieland , Sandor S. Kalman, III
发明人： Sankaranarayanan Srinivasan , W. Story Leavesley, III , George L. McHugh , Douglas P. Wieland , Sandor S. Kalman, III
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5054 , G06F17/5068
摘要： Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (504). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced (506) for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced (510, 512) for then instance of the pre-implemented circuit design using the first physical implementation.
摘要翻译：描述了用于实现可编程逻辑器件的预先实现的电路设计的方法和装置。在一个示例中，获得预先实现的电路设计的定义（504）。该定义包括第一物理实现和第一逻辑实现。对于使用第一逻辑实现的预先实现的电路设计的实例，产生第二逻辑实现（506）（506）。使用第一物理实现为第二物理实现（510,512）生成预实现电路设计的实例。

6. 发明授权

US08286113B1 Verification of logic core implementation 有权
标题翻译：验证逻辑核心实现
公开(公告)号：US08286113B1
公开(公告)日：2012-10-09
申请号：US13004183
申请日：2011-01-11
申请人： Brendan K. Bridgford , Jason J. Moore , W. Story Leavesley, III , Derrick S. Woods
发明人： Brendan K. Bridgford , Jason J. Moore , W. Story Leavesley, III , Derrick S. Woods
IPC分类号： G06F17/50 , G06F15/177 , G06F9/00
CPC分类号： G06F17/5022 , G06F17/5054 , G06F2217/66
摘要： A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.
摘要翻译：提供了一种用于验证完整比特流中的逻辑核的实现的系统和方法。从完整比特流中提取逻辑核心比特流。将逻辑核心比特流与用于目标设备的逻辑核心的参考比特流进行比较。响应于逻辑核心比特流和参考比特流的比较中没有差异，存储指示包含在完整比特流中的逻辑核心实现被验证的数据值。

7. 发明授权

US07619442B1 Versatile bus interface macro for dynamically reconfigurable designs 有权
标题翻译：用于动态可重构设计的多功能总线接口宏
公开(公告)号：US07619442B1
公开(公告)日：2009-11-17
申请号：US12180323
申请日：2008-07-25
申请人： Jeffrey M. Mason , W. Story Leavesley, III
发明人： Jeffrey M. Mason , W. Story Leavesley, III
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.
摘要翻译：描述了PLD中模块设计的方法和装置。在一个示例中，PLD包括可重配置模块，静态模块和至少一个逻辑接口宏。可重配置模块包括信号接口并被配置用于主动部分重配置。静态模块包括信号接口。每个逻辑接口宏包括耦合到可重构模块的信号接口的第一引脚和耦合到静态模块的信号接口的第二引脚。第一引脚和第二引脚设置在可重新配置模块的实现区域中。在一个实施例中，每个逻辑接口宏包括可配置逻辑块（CLB）的片。在一些实施例中，使用另一类型的逻辑块（诸如块RAM和/或乘法器块）来实现每个逻辑接口宏。

8. 发明授权

US07810055B1 Design independent correlation data storage for use with physical design of programmable logic devices 有权
标题翻译：设计独立的相关数据存储，用于可编程逻辑器件的物理设计
公开(公告)号：US07810055B1
公开(公告)日：2010-10-05
申请号：US11633962
申请日：2006-12-05
申请人： Brian J. Alexander , Jaime D. Lujan , W. Story Leavesley, III
发明人： Brian J. Alexander , Jaime D. Lujan , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing correlation data for a design implementation process can include identifying correlation data from each of a plurality of design applications. Each of the design applications can generate a circuit description and the correlation data can specify associations between circuit elements of different ones of the circuit descriptions. The method also can include storing the circuit descriptions and the correlation data independently of one another and determining a relationship among circuit elements of the circuit descriptions according to the correlation data.
摘要翻译：管理设计实现过程的相关数据的方法可以包括从多个设计应用中的每一个识别相关数据。每个设计应用可以产生电路描述，并且相关数据可以指定不同电路描述的电路元件之间的关联。该方法还可以包括彼此独立地存储电路描述和相关数据，并根据相关数据确定电路描述的电路元件之间的关系。

9. 发明授权

US07590951B1 Plug-in component-based dependency management for partitions within an incremental implementation flow 有权
标题翻译：在增量实现流程中为分区插件基于组件的依赖关系管理
公开(公告)号：US07590951B1
公开(公告)日：2009-09-15
申请号：US11500525
申请日：2006-08-08
申请人： William R. Bell, II , William W. Stiehl , Emil S. Ochotta , W. Story Leavesley, III
发明人： William R. Bell, II , William W. Stiehl , Emil S. Ochotta , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and, from a first application, invoking at least one plug-in software component configured to access the dependency management data for the circuit design. The method further can include identifying partitions of the circuit design that must be run during the incremental flow using the plug-in software component.
摘要翻译：管理电路设计的增量实现流程（增量流程）的方法可以包括存储用于电路设计的增量流的依赖性管理数据，并且从第一应用程序调用至少一个被配置为访问电路设计的依赖管理数据。该方法还可以包括识别在使用插件软件组件的增量流期间必须运行的电路设计的分区。

10. 发明授权

US07478357B1 Versatile bus interface macro for dynamically reconfigurable designs 有权
公开(公告)号：US07478357B1
公开(公告)日：2009-01-13
申请号：US11503589
申请日：2006-08-14
申请人： Jeffrey M. Mason , W. Story Leavesley, III
发明人： Jeffrey M. Mason , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.

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