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1. 发明授权

US08327199B1 Integrated circuit with configurable test pins 有权
标题翻译：具有可配置测试引脚的集成电路
公开(公告)号：US08327199B1
公开(公告)日：2012-12-04
申请号：US12718914
申请日：2010-03-05
申请人： Jayabrata Ghosh Dastidar , Chiew Khiang Kuit , Siew Ling Yeoh , Jun Pin Tan , Kok Sun Chia , Yee Liang Tan , Kar Keng Chua
发明人： Jayabrata Ghosh Dastidar , Chiew Khiang Kuit , Siew Ling Yeoh , Jun Pin Tan , Kok Sun Chia , Yee Liang Tan , Kar Keng Chua
IPC分类号： G01R31/28
CPC分类号： G01R31/3172 , G01R31/318516
摘要： Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.
摘要翻译：公开了具有可配置测试引脚的集成电路（IC）和测试IC的方法。 IC具有可配置为测试输入引脚，测试输出引脚或用户I / O引脚的输入/输出（I / O）引脚。选择器电路用于选择性地将I / O引脚路由和耦合到IC上的各种逻辑块和测试电路。选择器电路还用于选择性地将用户输出或测试输出耦合到IC上的不同I / O引脚。开关用于配置选择器电路并在IC内部路由测试信号。交换机的不同配置决定信号的路由。来自I / O引脚的测试输入信号可以被路由到IC内的任何测试电路，并且来自测试电路的测试输出信号可以被路由到IC上的任何I / O引脚。

2. 发明授权

US07761754B1 Techniques for testing memory circuits 失效
标题翻译：测试存储器电路的技术
公开(公告)号：US07761754B1
公开(公告)日：2010-07-20
申请号：US12055099
申请日：2008-03-25
申请人： Chin Hai Ang , Tze Sin Tan , Ala-Uddin Ismail , Siew Ling Yeoh
发明人： Chin Hai Ang , Tze Sin Tan , Ala-Uddin Ismail , Siew Ling Yeoh
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C8/06 , G11C29/12 , G11C29/1201 , G11C29/48
摘要： An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
摘要翻译：集成电路包括存储器电路，耦合到存储器电路的读取地址端口的读取地址寄存器，耦合到存储器电路的写入地址端口的写入地址寄存器，以及可配置为从读取地址寄存器将写入地址寄存器写入读取地址寄存器以响应读取控制信号。读取地址寄存器在存储器电路的测试期间通过读取地址端口将读取地址位加载到存储器电路中。集成电路可以包括可配置为响应于写入控制信号将写入地址位从读取地址寄存器传送到写入地址寄存器的多路复用器。写入地址寄存器在存储器电路的测试期间通过写入地址端口将写入地址位加载到存储器电路中。

3. 发明授权

US07984344B1 Techniques for testing memory circuits 有权
标题翻译：测试存储器电路的技术
公开(公告)号：US07984344B1
公开(公告)日：2011-07-19
申请号：US12839319
申请日：2010-07-19
申请人： Chin Hai Ang , Tze Sin Tan , Ala-Uddin Ismail , Siew Ling Yeoh
发明人： Chin Hai Ang , Tze Sin Tan , Ala-Uddin Ismail , Siew Ling Yeoh
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C8/06 , G11C29/12 , G11C29/1201 , G11C29/48
摘要： An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
摘要翻译：集成电路包括存储器电路，耦合到存储器电路的读取地址端口的读取地址寄存器，耦合到存储器电路的写入地址端口的写入地址寄存器，以及可配置为从读取地址寄存器将写入地址寄存器写入读取地址寄存器以响应读取控制信号。读取地址寄存器在存储器电路的测试期间通过读取地址端口将读取地址位加载到存储器电路中。集成电路可以包括可配置为响应于写入控制信号将写入地址位从读取地址寄存器传送到写入地址寄存器的多路复用器。写入地址寄存器在存储器电路的测试期间通过写入地址端口将写入地址位加载到存储器电路中。

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