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1. 发明授权

US08621303B1 Clock control circuitry and methods of utilizing the clock control circuitry 有权
公开(公告)号：US08621303B1
公开(公告)日：2013-12-31
申请号：US13354706
申请日：2012-01-20
申请人： Kalyana Ravindra Kantipudi , Dhwani Shah , Jayabrata Ghosh Dastidar
发明人： Kalyana Ravindra Kantipudi , Dhwani Shah , Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318536 , G01R31/318555 , G01R31/318572 , G06F1/04
摘要： A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.

2. 发明授权

US07266028B1 Method and apparatus for bit mapping memories in programmable logic device integrated circuits during at-speed testing 有权
标题翻译：用于在速度测试期间可编程逻辑器件集成电路中位映射存储器的方法和装置
公开(公告)号：US07266028B1
公开(公告)日：2007-09-04
申请号：US11357253
申请日：2006-02-16
申请人： Jayabrata Ghosh Dastidar
发明人： Jayabrata Ghosh Dastidar
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C2029/0401 , G11C2029/0405 , G11C2029/1208 , G11C2029/1806 , G11C2029/3602 , H03K19/1776 , H03K19/17764
摘要： Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in self test circuitry and address and data paths are formed by loading configuration data into a programmable logic device. During write operations on a memory block under test, test data words are written into the memory block. A comparator compares data words read from the memory block to expected data words received from the test pattern generator to produce corresponding comparison data words. The comparison data words are written into the shadow memory. The same addresses are applied to the memory block under test and the shadow memory, so the stored comparison data words form a test results bit map indicative of errors in the memory block.
摘要翻译：可编程逻辑器件可以在测试存储器块时使用影子存储器来收集诊断信息。可以在诸如最高允许时钟速度的系统中的正常操作期间允许的任何时钟速度下执行存储器块测试。内置自检电路，地址和数据路径是通过将配置数据加载到可编程逻辑器件中形成的。在对被测内存块进行写操作期间，将测试数据字写入存储块。比较器将从存储器块读取的数据字与从测试码型发生器接收到的预期数据字进行比较，以产生对应的比较数据字。比较数据字被写入阴影存储器。相同的地址被应用于被测存储块和影子存储器，所以存储的比较数据字形成指示存储器块中的错误的测试结果位图。

3. 发明授权

US07131043B1 Automatic testing for programmable networks of control signals 有权
标题翻译：自动测试控制信号的可编程网络
公开(公告)号：US07131043B1
公开(公告)日：2006-10-31
申请号：US10671891
申请日：2003-09-25
申请人： Jayabrata Ghosh Dastidar
发明人： Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28
CPC分类号： G01R31/31722 , G01R31/31723 , G01R31/318516
摘要： Techniques are provided for testing routing resources that route control signals on programmable integrated circuits (ICs). Control signals (such as clock signals) are routed through a logic gate to a test register. Values of the control signals are stored in the test register, transmitted outside the IC, and then compared to expected values to identify defects in the programmable interconnections. An enable circuit couples the control signals to functional registers on the programmable IC during user mode. The enable circuit decouples the control signals from the functional registers so that the control signals do not interfere with tests of the functional registers during test mode. During the test procedures, the control signals are treated as data signals and are not used to control other registers on the IC.
摘要翻译：提供了用于测试在可编程集成电路（IC）上路由控制信号的路由资源的技术。控制信号（例如时钟信号）通过逻辑门路由到测试寄存器。控制信号的值存储在测试寄存器中，在IC外传输，然后与预期值进行比较，以识别可编程互连中的缺陷。在用户模式期间，使能电路将控制信号耦合到可编程IC上的功能寄存器。使能电路将控制信号与功能寄存器分离，使得控制信号在测试模式期间不干扰功能寄存器的测试。在测试过程中，控制信号被视为数据信号，不用于控制IC上的其他寄存器。

4. 发明授权

US08952713B1 Method and apparatus for die testing 有权
标题翻译：模具测试的方法和设备
公开(公告)号：US08952713B1
公开(公告)日：2015-02-10
申请号：US13369224
申请日：2012-02-08
申请人： Jayabrata Ghosh Dastidar , Aman Aflaki Beni , Zunhang Yu Kasnavi
发明人： Jayabrata Ghosh Dastidar , Aman Aflaki Beni , Zunhang Yu Kasnavi
IPC分类号： G01R31/20
CPC分类号： G01R31/2886
摘要： A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.
摘要翻译：提供了一个设备测试仪。器件测试器包括探针卡和耦合到探针卡的衬底。衬底具有用于布线信号的多个层。集成电路耦合到衬底。集成电路可操作以将从测试装置接收的输入信号通过衬底传送到被测器件到信号探头。信号探头还可操作以响应于输入信号从被测器件接收测试信号，其中集成电路可操作以放大测试信号，并将放大的测试信号发送到测试设备。

5. 发明授权

US07996743B1 Logic circuit testing with reduced overhead 有权
标题翻译：逻辑电路测试，降低开销
公开(公告)号：US07996743B1
公开(公告)日：2011-08-09
申请号：US12060805
申请日：2008-04-01
申请人： Tze Sin Tan , Jayabrata Ghosh Dastidar
发明人： Tze Sin Tan , Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28 , G01R31/00 , G06F11/00 , G04F1/00
CPC分类号： G01R31/31727
摘要： An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.
摘要翻译：集成电路可能具有被测电路。集成电路可以具有从测试器接收参考时钟并且产生相应核心时钟的时钟产生电路。集成电路可以具有内置的自测电路和接收核心时钟的时钟合成器。内置的自测电路可以提供时钟合成器控制信号，其指示时钟合成器在各种测试时钟频率下产生测试时钟信号。在电路测试期间，测试时钟频率的测试时钟可能会被应用于被测电路。当电路测试成功完成时，被测电路可能会断言通过信号。内置的自检电路可能会通知测试人员测试电路成功通过测试的最大时钟频率。

6. 发明授权

US07424658B1 Method and apparatus for testing integrated circuits 有权
标题翻译：集成电路测试方法和装置
公开(公告)号：US07424658B1
公开(公告)日：2008-09-09
申请号：US10188162
申请日：2002-07-01
申请人： Jayabrata Ghosh Dastidar
发明人： Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318555
摘要： A technique and device for testing integrated circuits is implemented by comparing similar test outputs for differences. One particular type of integrated circuit that may benefit from this method of testing is a programmable logic integrated circuit. Separate logic units in the integrated circuit receive test patterns and generate outputs based on the test patterns. A comparator is then used to compare the outputs. If one output differs from the other outputs, an error message is created and test result information is stored in memory for use in pinpointing the cause of the error signal. In other embodiments, a microprocessor or embedded processor core may be configured to provide test patterns or used for comparison of the test pattern outputs.
摘要翻译：用于测试集成电路的技术和设备通过比较类似的测试输出来实现差异。可以受益于这种测试方法的一种特定类型的集成电路是可编程逻辑集成电路。集成电路中的单独逻辑单元接收测试模式，并根据测试模式生成输出。然后使用比较器来比较输出。如果一个输出与其他输出不同，则会产生错误信息，并将测试结果信息存储在存储器中，以便精确定位错误信号的原因。在其他实施例中，微处理器或嵌入式处理器核心可以被配置为提供测试模式或用于比较测试模式输出。

7. 发明授权

US07571413B1 Testing circuitry for programmable logic devices with selectable power supply voltages 有权
标题翻译：具有可选电源电压的可编程逻辑器件的测试电路
公开(公告)号：US07571413B1
公开(公告)日：2009-08-04
申请号：US11478148
申请日：2006-06-28
申请人： Jayabrata Ghosh Dastidar , Srinivas Perisetty , Andy L. Lee
发明人： Jayabrata Ghosh Dastidar , Srinivas Perisetty , Andy L. Lee
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： H03K19/17764 , G01R31/318516 , G01R31/318575 , H03K19/17744 , H03K19/17784
摘要： A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.
摘要翻译：可编程集成电路具有多个电源电压。使用电源配电线分配电源电压。集成电路具有可编程电源电压选择开关。每个电源电压选择开关的输入连接到电源配线，并将选定的电源电压提供给其输出端的电路块。提供测试电路用于测试电源电压选择开关。在测试期间，调整电源电压选择开关，以在其输出端产生各种电源电压。与每个开关相关的测试电路执行电压比较，以确定开关是否正常工作。每个测试电路基于其电压比较产生测试结果。将测试电路的测试结果提供给扫描链，该扫描链将测试结果从集成电路卸载到测试仪进行分析。

8. 发明授权

US07212032B1 Method and apparatus for monitoring yield of integrated circuits 有权
标题翻译：监测集成电路产量的方法和装置
公开(公告)号：US07212032B1
公开(公告)日：2007-05-01
申请号：US11411310
申请日：2006-04-25
申请人： Jayabrata Ghosh Dastidar , Laiq Chughtai , William Y. Hata
发明人： Jayabrata Ghosh Dastidar , Laiq Chughtai , William Y. Hata
IPC分类号： H03K19/173
CPC分类号： G01R31/31718
摘要： A method for analyzing a structured integrated circuit is provided. The method includes identifying a random logic region of the structured integrated circuit. The structured integrated circuit includes a predefined layout for transistors and basic interconnections to define a set of logic elements. A tile array of basic logic cells is integrated throughout the identified random logic region. The tile array of basic logic cells is defined from the set of logic elements of the structured integrated circuit. The tile array of basic cells enables communication of testing signals along the tile array of basic logic cells in a first and a second direction. The first and second directions are different from one another. The testing signals help to identify one or more errors in the tile array of basic logic cells. The array format assists in diagnosing and curing defects in the tile array of basic logic cells. The errors are pinpointed to a basic logic cell at the intersection of the first and second direction.
摘要翻译：提供了一种用于分析结构化集成电路的方法。该方法包括识别结构化集成电路的随机逻辑区域。结构化集成电路包括用于晶体管和基本互连的预定布局以定义一组逻辑元件。基本逻辑单元的瓦片阵列整合在所识别的随机逻辑区域中。基本逻辑单元的瓦片阵列由结构化集成电路的逻辑元件的集合来定义。基本单元的瓦片阵列使得能够沿着第一和第二方向沿着基本逻辑单元的瓦片阵列通信测试信号。第一和第二方向彼此不同。测试信号有助于识别基本逻辑单元的瓦片阵列中的一个或多个错误。阵列格式有助于诊断和修复基本逻辑单元的瓦片阵列中的缺陷。在第一和第二方向的交点处，精确地将错误定位到基本逻辑单元。

9. 发明授权

US07062685B1 Techniques for providing early failure warning of a programmable circuit 失效
标题翻译：提供可编程电路的早期故障警告的技术
公开(公告)号：US07062685B1
公开(公告)日：2006-06-13
申请号：US10317436
申请日：2002-12-11
申请人： Jordan Plofsky , Jayabrata Ghosh Dastidar , Michael Harms
发明人： Jordan Plofsky , Jayabrata Ghosh Dastidar , Michael Harms
IPC分类号： G06F11/00
CPC分类号： G01R31/318516 , G06F11/1423 , H03K19/177 , H03K19/17736
摘要： Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the components in memory. If the performance characteristics for particular components fall outside tolerance ranges, these components may to fail to operate according to specifications. Once the performance characteristics for particular components are outside the tolerance ranges, the processor sends out an alert signal. The alert signal indicates the possibility that the performance of the programmable circuit may violate the specifications in the future. The processor may repair the programmable circuit by re-routing around the problem components.
摘要翻译：提供了用于监视可编程电路的性能并提供潜在故障的早期警告的技术。处理器随时间监视可编程电路上的组件的性能。处理器存储内存中组件的性能特征。如果特定部件的性能特性落在公差范围之外，这些部件可能无法根据规格进行操作。一旦特定组件的性能特征超出公差范围，处理器就会发出警报信号。警报信号表示可编程电路的性能可能会违反将来的规格。处理器可以通过围绕问题组件重新路由来修复可编程电路。

10. 发明授权

US07058534B1 Method and apparatus for application specific test of PLDs 失效
标题翻译： PLD应用特异性检测方法和装置
公开(公告)号：US07058534B1
公开(公告)日：2006-06-06
申请号：US10394486
申请日：2003-03-19
申请人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
发明人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
IPC分类号： G01R31/00
CPC分类号： G01R31/318516
摘要： Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application is identified. A test is then performed only on the set and a test result is generated. Defective resources may be replaced. The PLD is identified as defective only if one of the resources associated with the customer application is defective. Such application specific testing allows the ability of the customer to perform in-system testing, the reduction of the time required for testing the PLD, and the testing of PLDs based on knowledge of the customer's application, among other advantages.
摘要翻译： PLD应用特定测试方法和设备。 PLD具有多个资源，少于用于实施客户应用程序的资源。该方法包括以下步骤。识别用于实现客户应用程序的一组资源。然后仅对集合进行测试，并生成测试结果。资源不足可能会被替换。只有当与客户应用程序相关联的资源之一有缺陷时，PLD才被识别为有缺陷。这样的应用程序特定测试允许客户执行系统测试，减少测试PLD所需的时间以及基于客户应用知识的PLD测试的能力等。

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