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1. 发明授权

US08880856B1 Efficient arithmetic logic units 有权
标题翻译：高效的算术逻辑单元
公开(公告)号：US08880856B1
公开(公告)日：2014-11-04
申请号：US12486114
申请日：2009-06-17
申请人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
发明人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
IPC分类号： G06F15/00
CPC分类号： G06F9/28 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F9/30018 , G06F9/30072 , G06F9/30145 , G06F9/3859 , G06F9/3893 , G06F15/00
摘要： A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.
摘要翻译：处理器可以包括条件算术逻辑单元和主算术逻辑单元。条件算术逻辑单元可以执行第一算术逻辑运算以产生第一结果，并输出结果。主算术逻辑单元可以选择携带来自条件算术逻辑单元的第一结果的多个数据总线中的输入总线，对由所选择的输入总线提供的数据执行第二运算逻辑运算以产生第二结果，并写入第二个结果是存储组件。

2. 发明授权

US08069023B1 Hardware support for instruction set emulation 有权
标题翻译：硬件支持指令集仿真
公开(公告)号：US08069023B1
公开(公告)日：2011-11-29
申请号：US12202742
申请日：2008-09-02
申请人： Jean-Marc Frailong , Jeffrey G. Libby , Jianhui Huang , Sharada Yeluri , Rajesh Nair , John Keen
发明人： Jean-Marc Frailong , Jeffrey G. Libby , Jianhui Huang , Sharada Yeluri , Rajesh Nair , John Keen
IPC分类号： G06F17/50
CPC分类号： G06F9/3004 , G06F9/30145 , G06F9/30174 , G06F9/32 , H04L45/745
摘要： A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.
摘要翻译：一种在专用硬件协助下仿真微代码中的下一跳指令的方法，用于从下一跳指令中提取读取和写入寻址，而不是在微码中执行该操作。一种在专用硬件的协助下仿真微代码中的下一跳指令的方法，用于将下一跳读取地址与特殊值进行比较，并指示下一跳读取地址是否匹配特殊值，而不是以微码执行该操作。一种通过执行树指令的位字段的单次提取来确定网络地址以允许执行多个树搜索处理的方法。

3. 发明授权

US09026424B1 Emulation of multiple instruction sets 有权
标题翻译：仿真多个指令集
公开(公告)号：US09026424B1
公开(公告)日：2015-05-05
申请号：US12258487
申请日：2008-10-27
申请人： Jeffrey G. Libby , Jean-Marc Frailong , Sharada Yeluri , Jianhui Huang , John Keen , Rajesh Nair
发明人： Jeffrey G. Libby , Jean-Marc Frailong , Sharada Yeluri , Jianhui Huang , John Keen , Rajesh Nair
IPC分类号： G06F9/455 , G06F12/00 , G06F17/50
CPC分类号： G06F9/455 , G06F9/45504 , G06F12/00 , G06F17/50
摘要： A device may emulate target instructions by executing a first set of microinstructions, and may store a base address of a table that includes a microinstruction provided in a second set of microinstructions for emulating the target instructions. The device may also locate the microinstruction based on the stored base address, and emulate one of the target instructions by executing the microinstruction.
摘要翻译：设备可以通过执行第一组微指令来模拟目标指令，并且可以存储包括在第二组微指令中提供的用于模拟目标指令的微指令的表的基地址。设备还可以基于存储的基地址定位微指令，并且通过执行微指令来模拟目标指令之一。

4. 发明授权

US08520675B1 System and method for efficient packet replication 有权
标题翻译：高效的数据包复制的系统和方法
公开(公告)号：US08520675B1
公开(公告)日：2013-08-27
申请号：US12343276
申请日：2008-12-23
申请人： Jean-Marc Frailong , Jeffrey G. Libby , Anurag P. Gupta , John Keen , Rajesh Nair , Avanindra Godbole , Sharada Yeluri
发明人： Jean-Marc Frailong , Jeffrey G. Libby , Anurag P. Gupta , John Keen , Rajesh Nair , Avanindra Godbole , Sharada Yeluri
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/56 , H04L45/16 , H04L49/10 , H04L49/90
摘要： Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.
摘要翻译：与本发明一致的方法和系统在路由器中提供有效的分组复制以便多播数据流。数据包在多线程环境中进行复制和处理。与本发明一致的实施例实现了用于分组复制的两阶段过程。第一级线程将数据包循环到多个第二级线程。这些第二级线程将会创建一个或多个数据包的输出副本。以这种方式，副本由并行运行的多个线程处理。

5. 发明授权

US08799909B1 System and method for independent synchronous and asynchronous transaction requests 有权
标题翻译：用于独立同步和异步事务请求的系统和方法
公开(公告)号：US08799909B1
公开(公告)日：2014-08-05
申请号：US12342985
申请日：2008-12-23
申请人： Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri , Anurag P. Gupta , John Keen
发明人： Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri , Anurag P. Gupta , John Keen
IPC分类号： G06F9/00 , G06F9/46
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3009
摘要： Systems and methods of various embodiments provide mechanisms to support synchronous and asynchronous transactions. Distinct encodings allow an instruction to choose whether to perform any operation synchronously or asynchronously. Separate synchronous and asynchronous result registers hold the data returned in the most recent replies received for synchronous and asynchronous transaction requests, respectively. A status bit indicates whether an asynchronous transaction request is currently outstanding.
摘要翻译：各种实施例的系统和方法提供了支持同步和异步事务的机制。不同的编码允许指令选择是同步还是异步执行任何操作。单独的同步和异步结果寄存器分别保存在同步和异步事务请求中接收的最近的回复中返回的数据。状态位指示异步事务请求当前是否未完成。

6. 发明申请

US20120084534A1 SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE 有权
标题翻译：使用可编程分支表快速分支的系统和方法
公开(公告)号：US20120084534A1
公开(公告)日：2012-04-05
申请号：US13323358
申请日：2011-12-12
申请人： Anurag P. GUPTA , John Keen , Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharida Yeluri
发明人： Anurag P. GUPTA , John Keen , Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharida Yeluri
IPC分类号： G06F9/38 , G06F9/32 , G06F9/312
CPC分类号： G06F9/30058 , G06F9/262 , G06F9/3885
摘要： Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.
摘要翻译：与本发明一致的方法和系统提供了可编程表，其允许软件定义多个分支功能，每个分支功能将条件代码的向量映射到分支偏移。该技术允许灵活的多路分支功能，使用可由程序员指定的条件分支结果表。任何指令都可以指定任意条件表达式的计算，以计算条件代码的值，并可以选择特定的分支函数。当处理器执行指令时，处理器的算术/逻辑功能单元评估条件表达式，然后处理器根据指定的分支函数执行分支操作。

7. 发明授权

US08078849B2 Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table 有权
标题翻译：使用可编程分支偏移表快速执行具有多个条件表达式的分支指令
公开(公告)号：US08078849B2
公开(公告)日：2011-12-13
申请号：US12342851
申请日：2008-12-23
申请人： Jeffrey G. Libby , Jean-Marc Frailong , Anurag P. Gupta , John Keen , Avanindra Godbole , Sharada Yeluri
发明人： Jeffrey G. Libby , Jean-Marc Frailong , Anurag P. Gupta , John Keen , Avanindra Godbole , Sharada Yeluri
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/262 , G06F9/3885
摘要： Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.
摘要翻译：与本发明一致的方法和系统提供了可编程表，其允许软件定义多个分支功能，每个分支功能将条件代码的向量映射到分支偏移。该技术允许灵活的多路分支功能，使用可由程序员指定的条件分支结果表。任何指令都可以指定任意条件表达式的计算，以计算条件代码的值，并可以选择特定的分支函数。当处理器执行指令时，处理器的算术/逻辑功能单元评估条件表达式，然后处理器根据指定的分支函数执行分支操作。

8. 发明授权

US08332622B2 Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction 有权
标题翻译：通过将从可编程偏移表中选择的值添加到分支指令中指定的基址来分支到目标地址
公开(公告)号：US08332622B2
公开(公告)日：2012-12-11
申请号：US13323358
申请日：2011-12-12
申请人： Anurag P Gupta , John Keen , Jeffrey G Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri
发明人： Anurag P Gupta , John Keen , Jeffrey G Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/262 , G06F9/3885
摘要： Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.
摘要翻译：与本发明一致的方法和系统提供了可编程表，其允许软件定义多个分支功能，每个分支功能将条件代码的向量映射到分支偏移。该技术允许灵活的多路分支功能，使用可由程序员指定的条件分支结果表。任何指令都可以指定任意条件表达式的计算，以计算条件代码的值，并可以选择特定的分支函数。当处理器执行指令时，处理器的算术/逻辑功能单元评估条件表达式，然后处理器根据指定的分支函数执行分支操作。

9. 发明申请

US20100161949A1 SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE 有权
标题翻译：使用可编程分支表快速分支的系统和方法
公开(公告)号：US20100161949A1
公开(公告)日：2010-06-24
申请号：US12342851
申请日：2008-12-23
申请人： Anurag P. Gupta , John Keen , Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri
发明人： Anurag P. Gupta , John Keen , Jeffrey G. Libby , Jean-Marc Frailong , Avanindra Godbole , Sharada Yeluri
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/262 , G06F9/3885
摘要： Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.
摘要翻译：与本发明一致的方法和系统提供了可编程表，其允许软件定义多个分支功能，每个分支功能将条件代码的向量映射到分支偏移。该技术允许灵活的多路分支功能，使用可由程序员指定的条件分支结果表。任何指令都可以指定任意条件表达式的计算，以计算条件代码的值，并可以选择特定的分支函数。当处理器执行指令时，处理器的算术/逻辑功能单元评估条件表达式，然后处理器根据指定的分支函数执行分支操作。

10. 发明授权

US08938469B1 Dynamically adjusting hash table capacity 有权
标题翻译：动态调整哈希表容量
公开(公告)号：US08938469B1
公开(公告)日：2015-01-20
申请号：US13239774
申请日：2011-09-22
申请人： John Keen , Jean-Marc Frailong , Deepak Goel
发明人： John Keen , Jean-Marc Frailong , Deepak Goel
IPC分类号： G06F17/30
CPC分类号： H04L45/7453
摘要： An example hashing unit includes a plurality of hardware-based hash tables, wherein each of the hash tables comprises a plurality of buckets, and wherein the plurality of hash tables comprise a set of zero or more active hash tables and a set of one or more inactive hash tables. An example hashing unit controller is configured to receive a key value to be stored in the hashing unit, determine that one of the inactive hash tables should be activated, and, based on the determination, activate the one of the set of inactive hash tables as a recently activated hash table, determine one of the buckets of the recently activated hash table to which a hash function associated with the recently activated hash table maps the received key value, and store the key value in the determined one of the buckets of the recently activated hash table.
摘要翻译：示例性散列单元包括多个基于硬件的散列表，其中每个散列表包括多个桶，并且其中所述多个散列表包括一组零个或多个活动散列表和一组一个或多个不活动的哈希表。示例性散列单元控制器被配置为接收要存储在散列单元中的密钥值，确定应激活其中一个非活动散列表，并且基于该确定，将该非活动散列表中的一个激活为最近激活的散列表确定最近激活的散列表的一个桶，其中与最近激活的散列表相关联的散列函数映射到接收到的密钥值，并将密钥值存储在最近确定的一个桶中激活哈希表。

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