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1. 发明授权

US08648391B2 SiGe heterojunction bipolar transistor with an improved breakdown voltage-cutoff frequency product 有权
标题翻译： SiGe异质结双极晶体管具有改进的击穿电压截止频率积
公开(公告)号：US08648391B2
公开(公告)日：2014-02-11
申请号：US13429262
申请日：2012-03-23
申请人： Jeffrey A. Babcock , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Alexei Sadovnikov
IPC分类号： H01L29/66
CPC分类号： H01L29/66242 , H01L21/76232 , H01L21/76283 , H01L27/0825 , H01L27/0826 , H01L29/0646 , H01L29/0649 , H01L29/0821 , H01L29/7371
摘要： The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
摘要翻译： SiGe异质结双极晶体管（HBT）的击穿电压（BVCEO）和截止频率（fT）的乘积通过利用具有从基极向下延伸的中空芯的掺杂区域而增加到约翰逊极限以上，掺杂的埋地集电区。掺杂区域和掩埋集电极区域具有相反的掺杂剂类型。

2. 发明授权

US08525233B1 SiGe heterojunction bipolar transistor with a shallow out-diffused P+ emitter region 有权
标题翻译： SiGe异质结双极晶体管，具有浅扩散的P +发射极区域
公开(公告)号：US08525233B1
公开(公告)日：2013-09-03
申请号：US13429274
申请日：2012-03-23
申请人： Jeffrey A. Babcock , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Alexei Sadovnikov
IPC分类号： H01L29/66
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826 , H01L29/0817 , H01L29/7378
摘要： A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
摘要翻译： pnp SiGe异质结双极晶体管（HBT）降低了晶体管的p +发射极中的p型掺杂剂原子通过外延生长发射极而扩散到晶体管的基极的低掺杂区域中的速率，以包括单晶锗区和上覆单晶硅区。

3. 发明申请

US20100032731A1 SCHOTTKY JUNCTION-FIELD-EFFECT-TRANSISTOR (JFET) STRUCTURES AND METHODS OF FORMING JFET STRUCTURES 有权
标题翻译：肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法
公开(公告)号：US20100032731A1
公开(公告)日：2010-02-11
申请号：US12498141
申请日：2009-07-06
申请人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov
IPC分类号： H01L29/80
CPC分类号： H01L27/095 , H01L27/0207 , H01L29/1029 , H01L29/1058 , H01L29/808 , H01L29/812
摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.
摘要翻译：根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接场效应晶体管（JFET）。在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

4. 发明授权

US08207559B2 Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures 有权
标题翻译：肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法
公开(公告)号：US08207559B2
公开(公告)日：2012-06-26
申请号：US12498141
申请日：2009-07-06
申请人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov , Zia Alan Shafi
发明人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov , Zia Alan Shafi
IPC分类号： H01L29/66
CPC分类号： H01L27/095 , H01L27/0207 , H01L29/1029 , H01L29/1058 , H01L29/808 , H01L29/812
摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.
摘要翻译：根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接场效应晶体管（JFET）。在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

5. 发明申请

US20130249057A1 SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH AN IMPROVED BREAKDOWN VOLTAGE-CUTOFF FREQUENCY PRODUCT 有权
标题翻译：具有改进的断开电压切断频率产品的异常双极晶体管
公开(公告)号：US20130249057A1
公开(公告)日：2013-09-26
申请号：US13429262
申请日：2012-03-23
申请人： Jeffrey A. Babcock , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Alexei Sadovnikov
IPC分类号： H01L29/70 , H01L21/328
CPC分类号： H01L29/66242 , H01L21/76232 , H01L21/76283 , H01L27/0825 , H01L27/0826 , H01L29/0646 , H01L29/0649 , H01L29/0821 , H01L29/7371
摘要： The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
摘要翻译： SiGe异质结双极晶体管（HBT）的击穿电压（BVCEO）和截止频率（fT）的乘积通过利用具有从基极向下延伸的中空芯的掺杂区域而增加到约翰逊极限以上，掺杂的埋地集电区。掺杂区域和掩埋集电极区域具有相反的掺杂剂类型。

6. 发明申请

US20130248935A1 SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH A SHALLOW OUT-DIFFUSED P+ EMITTER REGION 有权
标题翻译：信号异常双极晶体管，具有一个外部扩散的P +发射极区域
公开(公告)号：US20130248935A1
公开(公告)日：2013-09-26
申请号：US13429274
申请日：2012-03-23
申请人： Jeffrey A. Babcock , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Alexei Sadovnikov
IPC分类号： H01L29/737 , H01L21/20
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826 , H01L29/0817 , H01L29/7378
摘要： A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
摘要翻译： pnp SiGe异质结双极晶体管（HBT）降低了晶体管的p +发射极中的p型掺杂剂原子通过外延生长发射极而扩散到晶体管的基极的低掺杂区域中的速率，以包括单晶锗区和上覆单晶硅区。

7. 发明授权

US07714355B1 Method of controlling the breakdown voltage of BSCRs and BJT clamps 有权
标题翻译：控制BSCR和BJT夹具击穿电压的方法
公开(公告)号：US07714355B1
公开(公告)日：2010-05-11
申请号：US11312704
申请日：2005-12-20
申请人： Vladislav Vashchenko , Alexei Sadovnikov , Peter J. Hopper , Andy Strachan
发明人： Vladislav Vashchenko , Alexei Sadovnikov , Peter J. Hopper , Andy Strachan
IPC分类号： H01L29/74
CPC分类号： H01L29/7322 , H01L29/0821 , H01L29/74
摘要： In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
摘要翻译：在BSCR或BJT ESD钳位中，通过屏蔽收集器的一部分来控制BJT器件的集电极的尺寸来控制击穿电压和直流电压公差。

8. 发明授权

US06528862B1 Bipolar transistor with a box-type germanium profile that lies outside of the emitter-base depletion region 有权
标题翻译：位于发射极 - 基极耗尽区之外的具有盒型锗分布的双极晶体管
公开(公告)号：US06528862B1
公开(公告)日：2003-03-04
申请号：US10125897
申请日：2002-04-19
申请人： Alexei Sadovnikov
发明人： Alexei Sadovnikov
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The upper epitaxial layer of a bipolar transistor has a silicon germanium layer and an overlying cap layer. The upper epitaxial layer includes an intrinsic emitter region and a base region. The silicon germanium layer is spaced apart from the intrinsic emitter region, and lies outside of the depletion region associated with the junction between the intrinsic emitter region and the base region.
摘要翻译：双极晶体管的上部外延层具有硅锗层和上覆盖层。上部外延层包括本征发射极区域和基极区域。硅锗层与本征发射极区域间隔开，并且位于与本征发射极区域和基极区域之间的结点相关联的耗尽区域的外部。

9. 发明申请

US20100127352A1 SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE 有权
标题翻译：自对准双极晶体管结构
公开(公告)号：US20100127352A1
公开(公告)日：2010-05-27
申请号：US12692892
申请日：2010-01-25
申请人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
发明人： Monir El-Diwany , Alexei Sadovnikov , Jamal Ramdani
IPC分类号： H01L29/732 , H01L29/73
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7378
摘要： A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.
摘要翻译：双极晶体管结构包括具有第一导电类型的半导体衬底，具有与在形成于半导体衬底的上表面中的隔离电介质材料限定的衬底有源器件区域中形成的第一导电类型相反的第二导电类型的集电极区域包括在集电极区域上形成的具有第一导电类型的本征基极区域和形成在隔离电介质材料上的具有第二导电类型的非本征基极区域的基极区域和具有第二导电性的倾斜的原位掺杂发射极插塞形成在本征基区上。

10. 发明授权

US06967144B1 Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base 有权
标题翻译：用于减少具有选择性生长的外延基极的双极晶体管中发射极 - 基极电容的低掺杂基极间隔物
公开(公告)号：US06967144B1
公开(公告)日：2005-11-22
申请号：US10669045
申请日：2003-09-23
申请人： Alexei Sadovnikov
发明人： Alexei Sadovnikov
IPC分类号： H01L21/331 , H01L27/082 , H01L27/102 , H01L29/10 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66242 , H01L29/1004
摘要： A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type opposite the first conductivity type formed on the collector region and a relatively low doped (or undoped) upper layer formed on the highly doped lower layer. An emitter region having the first conductivity type is formed on the upper layer of the base region.
摘要翻译：双极晶体管结构包括在半导体衬底中形成的具有第一导电类型的集电极区域。在集电极区域上形成基极区域; 基极区域包括具有与集电极区域上形成的第一导电类型相反的第二导电类型的高度掺杂的下层，以及形成在高掺杂的下层上的相对较低的掺杂（或未掺杂的）上层。具有第一导电类型的发射极区域形成在基极区域的上层。

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