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1. 发明申请

US20120286838A1 DELAY LINE CIRCUIT AND PHASE INTERPOLATION MODULE THEREOF 有权
标题翻译：延迟线电路及其相位插值模块
公开(公告)号：US20120286838A1
公开(公告)日：2012-11-15
申请号：US13104034
申请日：2011-05-10
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： H03H11/26 , H03H11/16
CPC分类号： H03H11/265
摘要： A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals.
摘要翻译：提出了包括第一，第二和第三相位插值单元的相位插值模块。第一，第二和第三相位插值单元中的每一个包括第一至第三反相器，第一和第二电阻器，其中第一电阻器耦合在第一反相器的输出端和第三反相器的输入端之间，第二电阻耦合在第二反相器的输出端和第三反相器的输入端之间。第一相位插值单元的第一和第二反相器接收第一信号，第三相位插值单元的第一和第二反相器接收第二信号，第二相位插值单元的第一和第二反相器分别接收第一和第二相位插值单元信号。

2. 发明授权

US07002870B2 Speeding up the power-up procedure for low power RAM 有权
标题翻译：加快低功耗RAM的上电程序
公开(公告)号：US07002870B2
公开(公告)日：2006-02-21
申请号：US10861162
申请日：2004-06-04
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C2207/2227
摘要： An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.
摘要翻译：描述了用于低功率存储器芯片的内部电力系统，其在芯片上电期间和在执行存储器操作的活动状态期间提供大容量内部电源。存储器芯片待机状态允许在大容量电源关闭的情况下降低芯片功率，并且存储器芯片内部电压由小容量电源提供。通过打开和关闭待机信号来实现低功耗存储器芯片的待机状态和有效状态之间的切换。在芯片上电期间，内部和外部芯片电压被监控，以确保在关闭大容量电源并将芯片置于待机状态之前达到预定的电压电平。

3. 发明申请

US20120287737A1 REPAIRING CIRCUIT FOR MEMORY CIRCUIT AND METHOD THEREOF AND MEMORY CIRCUIT USING THE SAME 有权
标题翻译：用于存储器电路的修复电路及其使用方法和存储器电路
公开(公告)号：US20120287737A1
公开(公告)日：2012-11-15
申请号：US13104038
申请日：2011-05-10
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C29/04
CPC分类号： G11C29/34 , G11C11/401 , G11C29/44 , G11C29/808
摘要： A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.
摘要翻译：通过本发明的实施例提供了一种新颖的修复方法和电路，其中可以使用输入/输出（IO）压缩方式来减少芯片探测1（CP1）测试期间的访问时间，并且选择每个冗余列线（RCSL）可以分为几个部分冗余列选择线（P-RCSL），分别负责修复相应区域的缺陷。基于修复方法，存储电路可以减少RCSL的数量。此外，应用可变区域分割方式，以增加修复存储电路的缺陷的可能性。

4. 发明授权

US08289795B1 Semiconductor memory device and method of testing the same 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US08289795B1
公开(公告)日：2012-10-16
申请号：US13270196
申请日：2011-10-10
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C29/34 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor memory device and a method of testing the same are provided. In the method, the semiconductor memory device enters a test mode after receiving a mode selection signal. After the semiconductor memory device enters the test mode, a first word line is activated. Test data are then sequentially written into a plurality of memory cells coupled to the first word line. The first word line is deactivated, and data between each pair of bit lines are latched. A second word line is activated. After the second word line is activated, the data latched between each pair of bit lines are directly written into the memory cells coupled to the second word line.
摘要翻译：提供半导体存储器件及其测试方法。在该方法中，半导体存储器件在接收到模式选择信号之后进入测试模式。在半导体存储器件进入测试模式之后，第一字线被激活。然后将测试数据顺序写入耦合到第一字线的多个存储单元。第一个字线被禁用，并且每对位线之间的数据被锁存。第二个字线被激活。在第二字线被激活之后，锁存在每对位线之间的数据被直接写入耦合到第二字线的存储单元中。

5. 发明授权

US07623388B2 Method for detecting erroneous word lines of a memory array and device thereof 有权
公开(公告)号：US07623388B2
公开(公告)日：2009-11-24
申请号：US12116197
申请日：2008-05-06
申请人： Tzu-Hao Chen , Jen-Shou Hsu , Lien-Sheng Yang , Yin-Ming Lan
发明人： Tzu-Hao Chen , Jen-Shou Hsu , Lien-Sheng Yang , Yin-Ming Lan
IPC分类号： G11C11/34
CPC分类号： G11C11/408 , G11C11/401 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum.

6. 发明申请

US20080174360A1 Charge pump circuit for high voltage generation 有权
标题翻译：电荷泵电路用于高压发电
公开(公告)号：US20080174360A1
公开(公告)日：2008-07-24
申请号：US11656733
申请日：2007-01-23
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/077
摘要： A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for eliminating threshold voltage drop losses and thus improves the voltage pumping gain compared to circuits with diode-configured FETs of prior art. Making use of voltage signals from antecedent stages in order to bias the bulk of MOS transistors fabricated in triple-well technology enables relaxing of the gate oxide stress within high order stage MOS transistors. Such a method, called leap-frog bulk potential tracking method, makes MOS transistors from different stages exhibit about the same body effect, which is very important because MOS transistors of higher order stages now show the same performance as MOS transistors from lower order stages. Important also in terms of efficiency as the charge sharing speed of high order MOS transistors always dominates the total charge pump performance and the driving force of pumped currents, thus also allowing for a greater number of serially connectable stages overall or a smaller number necessary for a certain targeted output voltage.
摘要翻译：给出了一种电路和方法，以实现集成电路的高效率电压倍增器，从低的外部正或负电源电压或接地产生内部和灵活的正或负高压片上电源电压。将多相控制信号施加到升压内部节点允许消除阈值电压降损耗，因此与现有技术的具有二极管配置的FET的电路相比，提高了电压泵浦增益。利用来自前级的电压信号，以偏置三重阱技术制造的MOS晶体管的大部分，可以缓解高阶MOS晶体管内的栅氧化层应力。这种称为跨跳体积电位跟踪方法的方法使得来自不同阶段的MOS晶体管呈现出相同的体效应，这是非常重要的，因为高阶级的MOS晶体管现在与低阶级的MOS晶体管具有相同的性能。在效率方面也是重要的，因为高阶MOS晶体管的电荷共享速度总是占据总电荷泵性能和泵浦电流的驱动力，因此还允许更多数量的可串行连接级或更少数量的某些有针对性的输出电压。

7. 发明授权

US08384459B2 Delay line circuit and phase interpolation module thereof 有权
标题翻译：延迟线电路及其相位插补模块
公开(公告)号：US08384459B2
公开(公告)日：2013-02-26
申请号：US13104034
申请日：2011-05-10
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： H03H11/16
CPC分类号： H03H11/265
摘要： A phase interpolation module comprising a first, second, and third phase interpolation units is proposed. Each of the first, second, and third phase interpolation units comprises a first through third inverters, a first and second resistors, wherein the first resistor is coupled between an output end of the first inverter and an input end of the third inverter, and the second resistor is coupled between an output end of the second inverter and the input end of the third inverter. The first and second inverters of the first phase interpolation unit receive a first signal, the first and second inverters of the third phase interpolation unit receive a second signal, and the first and second inverters of the second phase interpolation unit respectively receive the first and second signals.
摘要翻译：提出了包括第一，第二和第三相位内插单元的相位插值模块。第一，第二和第三相位插值单元中的每一个包括第一至第三反相器，第一和第二电阻器，其中第一电阻器耦合在第一反相器的输出端和第三反相器的输入端之间，第二电阻耦合在第二反相器的输出端和第三反相器的输入端之间。第一相位插值单元的第一和第二反相器接收第一信号，第三相位插值单元的第一和第二反相器接收第二信号，第二相位插值单元的第一和第二反相器分别接收第一和第二相位插值单元信号。

8. 发明申请

US20050270881A1 SPEEDING UP THE POWER-UP PROCEDURE FOR LOW POWER RAM 有权
标题翻译：加快低功耗RAM的加电程序
公开(公告)号：US20050270881A1
公开(公告)日：2005-12-08
申请号：US10861162
申请日：2004-06-04
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C7/20 , G11C19/08
CPC分类号： G11C7/20 , G11C2207/2227
摘要： An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power where the large capacity power source is turned off, and the memory chip internal voltages are provided by a small capacity power source. Switching between the standby and active states of the low power memory chip is accomplished by turning on and off a standby signal. The internal and external chip voltages are monitored during chip power up to insure that predetermined voltage levels have been reached before turning off the large capacity power source and placing the chip into a standby state.
摘要翻译：描述了用于低功率存储器芯片的内部电力系统，其在芯片上电期间和在执行存储器操作的活动状态期间提供大容量内部电源。存储器芯片待机状态允许在大容量电源关闭的情况下降低芯片功率，并且存储器芯片内部电压由小容量电源提供。通过打开和关闭待机信号来实现低功耗存储器芯片的待机状态和有效状态之间的切换。在芯片上电期间，内部和外部芯片电压被监控，以确保在关闭大容量电源并将芯片置于待机状态之前达到预定的电压电平。

9. 发明授权

US08472265B2 Repairing circuit for memory circuit and method thereof and memory circuit using the same 有权
标题翻译：用于存储器电路的修复电路及其方法和使用其的存储器电路
公开(公告)号：US08472265B2
公开(公告)日：2013-06-25
申请号：US13104038
申请日：2011-05-10
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C7/06 , G11C29/00 , G11C17/18 , G11C8/00
CPC分类号： G11C29/34 , G11C11/401 , G11C29/44 , G11C29/808
摘要： A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.
摘要翻译：通过本发明的实施例提供了一种新颖的修复方法和电路，其中可以使用输入/输出（IO）压缩方式来减少芯片探测1（CP1）测试期间的访问时间，并且选择每个冗余列线（RCSL）可以分为几个部分冗余列选择线（P-RCSL），分别负责修复相应区域的缺陷。基于修复方法，存储电路可以减少RCSL的数量。此外，应用可变区域分割方式，以增加修复存储电路的缺陷的可能性。

10. 发明授权

US07796448B2 Trigger circuit of a column redundant circuit and related column redundant device 有权
标题翻译：列冗余电路和相关列冗余设备的触发电路
公开(公告)号：US07796448B2
公开(公告)日：2010-09-14
申请号：US12257408
申请日：2008-10-24
申请人： Jen-Shou Hsu
发明人： Jen-Shou Hsu
IPC分类号： G11C16/04
CPC分类号： G11C29/808
摘要： A trigger circuit for triggering corresponding memory cells of a column redundant circuit includes a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address.
摘要翻译：用于触发列冗余电路的相应存储单元的触发电路包括：一个确定电路，用于根据访问的行地址产生一个确定信号;以及多个比较电路，它们共同电连接到列冗余电路，用于接收该确定信号，每个所述比较电路根据所述确定信号和所访问的列地址向所述列冗余电路选择性地产生触发信号。

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