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    • 5. 发明授权
    • Multiple power supplies for the driving circuit of local word line driver of DRAM
    • 用于DRAM的本地字线驱动器的驱动电路的多个电源
    • US07277315B2
    • 2007-10-02
    • US11304416
    • 2005-12-14
    • Der-Min YuanJen Shou HsuYao Yi Liu
    • Der-Min YuanJen Shou HsuYao Yi Liu
    • G11C11/24
    • G11C8/08G11C5/145G11C11/4074G11C11/4085
    • Methods and circuits to reduce power consumption of DRAM local word-line drivers are disclosed. A first voltage converter provides a voltage VPP1, which is lower than the voltage VPP required to operate a word-line of a DRAM cell array. A voltage detector monitors the voltage level of the local word-line driver. Once the voltage level VPP1 is reached on the local word-linedriver switching means as e.g. tri-state drivers put the final VPP voltage on the word line. This VPP voltage is the output of a second voltage boost converter. Putting the voltage in two stages on the word-line reduces the overall power consumption. The voltage level VPP1 has to be carefully selected to find a compromised solution between current consumption and performance.
    • 公开了减少DRAM本地字线驱动器功耗的方法和电路。 第一电压转换器提供低于操作DRAM单元阵列的字线所需的电压VPP的电压VPP 1。 电压检测器监视本地字线驱动器的电压电平。 一旦在本地的字形内部驱动器切换装置上达到电压电平VPP 1,例如, 三态驱动器将最终的VPP电压放在字线上。 该VPP电压是第二升压转换器的输出。 在字线上分两级进行电压降低了整体功耗。 必须仔细选择电压电平VPP 1以在电流消耗和性能之间找到一个受损的解决方案。
    • 8. 发明授权
    • Semiconductor memory device and method of testing the same
    • 半导体存储器件及其测试方法
    • US08289795B1
    • 2012-10-16
    • US13270196
    • 2011-10-10
    • Jen-Shou Hsu
    • Jen-Shou Hsu
    • G11C7/00
    • G11C29/08G11C29/34G11C2029/1202G11C2029/2602
    • A semiconductor memory device and a method of testing the same are provided. In the method, the semiconductor memory device enters a test mode after receiving a mode selection signal. After the semiconductor memory device enters the test mode, a first word line is activated. Test data are then sequentially written into a plurality of memory cells coupled to the first word line. The first word line is deactivated, and data between each pair of bit lines are latched. A second word line is activated. After the second word line is activated, the data latched between each pair of bit lines are directly written into the memory cells coupled to the second word line.
    • 提供半导体存储器件及其测试方法。 在该方法中,半导体存储器件在接收到模式选择信号之后进入测试模式。 在半导体存储器件进入测试模式之后,第一字线被激活。 然后将测试数据顺序写入耦合到第一字线的多个存储单元。 第一个字线被禁用,并且每对位线之间的数据被锁存。 第二个字线被激活。 在第二字线被激活之后,锁存在每对位线之间的数据被直接写入耦合到第二字线的存储单元中。