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1. 发明申请

US20120025890A1 Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair 有权
标题翻译：用于防止比较器差分输入晶体管对中的基极 - 发射极结反向偏置的电路和方法
公开(公告)号：US20120025890A1
公开(公告)日：2012-02-02
申请号：US12804658
申请日：2010-07-27
申请人： Jerry L. Doorenbos , Sudarshan Udayashankar
发明人： Jerry L. Doorenbos , Sudarshan Udayashankar
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.
摘要翻译：差分输入电路（1-1）包括分别与第一（Vin +）和第二（Vin-）输入信号耦合的控制电极的第一（Q0）和第二（Q1）输入晶体管。传输晶体管（P3）耦合在第一和第二输入晶体管的第一电极之间。第一（N1）和第二（N2）电平移位晶体管分别具有耦合到第一和第二输入信号的控制电极。电压选择器电路22选择第一和第二电平移位晶体管中的一个的第一电极上的电压，该电压处于较高电压，并且在传输晶体管的控制电极上产生相应的控制电压（V19）以便响应于第一和第二输入信号之间的大的差异来限制第一输入晶体管（Q0）的第一电极和控制电极关断时的电压差。

2. 发明授权

US08164364B2 Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair 有权
公开(公告)号：US08164364B2
公开(公告)日：2012-04-24
申请号：US12804658
申请日：2010-07-27
申请人： Jerry L. Doorenbos , Sudarshan Udayashankar
发明人： Jerry L. Doorenbos , Sudarshan Udayashankar
IPC分类号： H03K5/22
CPC分类号： H03K5/08
摘要： A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.

3. 发明申请

US20120025891A1 Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method 有权
标题翻译：双极晶体管抗饱和钳使用辅助双极级，和方法
公开(公告)号：US20120025891A1
公开(公告)日：2012-02-02
申请号：US12804752
申请日：2010-07-28
申请人： Sudarshan Udayashankar , Jerry L. Doorenbos
发明人： Sudarshan Udayashankar , Jerry L. Doorenbos
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
摘要翻译：输出级（1-2）包括用于驱动具有集电极的主晶体管（Q3）的基极的增益电路（Q1，Q2），其响应于输入信号V11而耦合到输出端（18），该输入信号也控制具有耦合到输出的集电极的辅助晶体管（Q7）的基极。钳位晶体管（Q6）具有耦合到辅助晶体管的基极的控制电极，耦合到输出的第一电极和耦合以提供从输出经由增益电路到主晶体管的基极的反馈的第二电极，以及以提供从输出到辅助晶体管的基极的反馈。当辅助晶体管进入深饱和时，使钳位晶体管从输出到主输出级提供负反馈，以防止主晶体管进入深饱和。

4. 发明授权

US08610484B2 Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method 有权
标题翻译：双极晶体管抗饱和钳使用辅助双极级，和方法
公开(公告)号：US08610484B2
公开(公告)日：2013-12-17
申请号：US12804752
申请日：2010-07-28
申请人： Sudarshan Udayashankar , Jerry L. Doorenbos
发明人： Sudarshan Udayashankar , Jerry L. Doorenbos
IPC分类号： H03K5/08 , H03F3/16
CPC分类号： H03K5/08
摘要： An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
摘要翻译：输出级（1-2）包括用于驱动具有集电极的主晶体管（Q3）的基极的增益电路（Q1，Q2），其响应于输入信号V11而耦合到输出端（18），该输入信号也控制具有耦合到输出的集电极的辅助晶体管（Q7）的基极。钳位晶体管（Q6）具有耦合到辅助晶体管的基极的控制电极，耦合到输出的第一电极和耦合以提供从输出经由增益电路到主晶体管的基极的反馈的第二电极，以及以提供从输出到辅助晶体管的基极的反馈。当辅助晶体管进入深饱和时，使钳位晶体管从输出端向主输出级提供负反馈，以防止主晶体管进入深饱和。

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