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1. 发明授权

US08308358B2 Circuit and method for beta variation compensation in single-transistor temperature sensor 有权
标题翻译：单晶体管温度传感器中β变换补偿的电路和方法
公开(公告)号：US08308358B2
公开(公告)日：2012-11-13
申请号：US12456991
申请日：2009-06-25
申请人： Jerry L. Doorenbos
发明人： Jerry L. Doorenbos
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , H03F1/302 , H03F2200/447 , H03F2200/468
摘要： A circuit (1-2) for compensating for variations in the current gain β of a sensing transistor (Q1) having a collector coupled to a reference voltage (GND) includes a first current mirror (20) having an input coupled to a base of the sensing transistor. A second current mirror (21) has an input coupled to an output of the first current mirror. A current source (13) is coupled to provide emitter current for the sensing transistor. An output of the second current mirror circuit (21) feeds base current of the sensing transistor back to its emitter to cause the collector current of the sensing transistor to be precisely equal to the current (I1) provided by the current source.
摘要翻译：用于补偿电流增益变化的电路（1-2）具有耦合到参考电压（GND）的集电极的感测晶体管（Q1）包括具有耦合到感测晶体管的基极的输入的第一电流镜（20）。第二电流镜（21）具有耦合到第一电流镜的输出的输入。电流源（13）被耦合以提供感测晶体管的发射极电流。第二电流镜电路（21）的输出将感测晶体管的基极电流反馈到其发射极，以使感测晶体管的集电极电流精确地等于由电流源提供的电流（I1）。

2. 发明授权

US08164364B2 Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair 有权
公开(公告)号：US08164364B2
公开(公告)日：2012-04-24
申请号：US12804658
申请日：2010-07-27
申请人： Jerry L. Doorenbos , Sudarshan Udayashankar
发明人： Jerry L. Doorenbos , Sudarshan Udayashankar
IPC分类号： H03K5/22
CPC分类号： H03K5/08
摘要： A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.

3. 发明申请

US20120025891A1 Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method 有权
标题翻译：双极晶体管抗饱和钳使用辅助双极级，和方法
公开(公告)号：US20120025891A1
公开(公告)日：2012-02-02
申请号：US12804752
申请日：2010-07-28
申请人： Sudarshan Udayashankar , Jerry L. Doorenbos
发明人： Sudarshan Udayashankar , Jerry L. Doorenbos
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
摘要翻译：输出级（1-2）包括用于驱动具有集电极的主晶体管（Q3）的基极的增益电路（Q1，Q2），其响应于输入信号V11而耦合到输出端（18），该输入信号也控制具有耦合到输出的集电极的辅助晶体管（Q7）的基极。钳位晶体管（Q6）具有耦合到辅助晶体管的基极的控制电极，耦合到输出的第一电极和耦合以提供从输出经由增益电路到主晶体管的基极的反馈的第二电极，以及以提供从输出到辅助晶体管的基极的反馈。当辅助晶体管进入深饱和时，使钳位晶体管从输出到主输出级提供负反馈，以防止主晶体管进入深饱和。

4. 发明申请

US20080259989A1 Systems and Methods for Temperature Measurement Using N-Factor Coefficient Correction 有权
标题翻译：使用N因子系数校正进行温度测量的系统和方法
公开(公告)号：US20080259989A1
公开(公告)日：2008-10-23
申请号：US11738595
申请日：2007-04-23
申请人： Jerry L. Doorenbos , Marco A. Gardner
发明人： Jerry L. Doorenbos , Marco A. Gardner
IPC分类号： G01K7/00 , G01K15/00
CPC分类号： G01K7/01 , G01K15/00 , G01K2219/00
摘要： Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a variable current source and a diode connected transistor. The variable current source is capable of applying two or more distinct currents to the diode connected transistor. The currents result in a different base-emitter voltage on the diode connected transistor. The systems further include an n-factor coefficient register and an analog to digital converter. The analog to digital converter is operable to receive two of the base-emitter voltages created by applying the different currents, and to provide a digital output based at least in part on a value stored in the n-factor coefficient register and the two base-emitter voltages.
摘要翻译：公开了用于温度测量的各种系统和方法。例如，本发明的一些实施例提供温度测量系统。这种温度测量系统包括可变电流源和二极管连接的晶体管。可变电流源能够向二极管连接的晶体管施加两个或更多个不同的电流。电流导致二极管连接晶体管上的基极 - 发射极电压不同。该系统还包括一个n因子系数寄存器和一个模数转换器。模数转换器可操作以接收通过施加不同电流产生的两个基极 - 发射极电压，并且至少部分地基于存储在n因子系数寄存器中的值和两个基极 - 发射极电压。

5. 发明授权

US08806083B2 Identification address configuration circuit and method without use of dedicated address pins 有权
标题翻译：识别地址配置电路和方法，不使用专用地址引脚
公开(公告)号：US08806083B2
公开(公告)日：2014-08-12
申请号：US11803465
申请日：2007-05-15
申请人： Jerry L. Doorenbos
发明人： Jerry L. Doorenbos
IPC分类号： G06F3/00 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4291
摘要： An identification address of a sensor interface device is configured in response to the order of connection of first (DXP1) and second (DXN1) package pins to electrodes of a sensor (Q0). A sensor signal processing circuit (23) has first and second inputs coupled through the first and second pins to the sensor for converting a parameter sensed by the sensor to a different representation. A current is forced through the first pin to produce either a high or low voltage on the first pin depending on the order of connection of the first and second pins to the electrodes of the sensor. A voltage on the first pin is compared with a reference voltage to produce a comparison signal which is mapped to produce the identification address.
摘要翻译：响应于第一（DXP1）和第二（DXN1）封装引脚到传感器（Q0）的电极的连接顺序来配置传感器接口装置的识别地址。传感器信号处理电路（23）具有通过第一和第二引脚耦合到传感器的第一和第二输入，用于将由传感器感测的参数转换成不同的表示。根据第一和第二引脚与传感器的电极的连接顺序，迫使电流通过第一引脚产生第一引脚上的高电压或低电压。将第一引脚上的电压与参考电压进行比较，以产生映射以产生识别地址的比较信号。

6. 发明申请

US20080258959A1 Integrating/SAR ADC and method with low integrator swing and low complexity 有权
标题翻译：集成/ SAR ADC和低积分摆幅和低复杂度的方法
公开(公告)号：US20080258959A1
公开(公告)日：2008-10-23
申请号：US12072968
申请日：2008-02-29
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/46 , H03M3/46
摘要： A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
摘要翻译：可重新配置电路（10）包括具有用于选择性地将输入电容器（C 0,1,2,3,6,7）和积分电容器（C 4,5）耦合到端子的开关（SW1-6）的积分器（30）用于操作混合Δ-Σ/ SAR ADC（400）的积分器（30），以便产生等于第一电压（DeltaVbe）和第二电压（Vbe）之和的参考电压值（Vref）。执行第一次积分以减小积分器输出电压摆幅。如果比较器（22）耦合到积分器，则如果比较器不改变状态，则将第二电压（Vbe）积分在第一方向上。如果比较器（22）耦合到积分器，则将积分器的残差（Vresidue）乘以2.然后，。第一电压（DeltaVbe）集成在使积分器输出电压（Vout）等于2xVresidue-Vref或2xVresidue + Vref的方向上。

7. 发明申请

US20080258951A1 Hybrid Delta-Sigma/SAR Analog to Digital Converter and Methods for Using Such 有权
标题翻译：混合Delta-Sigma / SAR模数转换器及其使用方法
公开(公告)号：US20080258951A1
公开(公告)日：2008-10-23
申请号：US11738566
申请日：2007-04-23
申请人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
发明人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
IPC分类号： H03M3/00
CPC分类号： H03M1/145 , H03M1/46 , H03M3/43 , H03M3/456 , H03M3/46
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译：公开了用于捕获数据的各种系统和方法。例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。

8. 发明授权

US09128571B2 Capacitive touch panel having improved response characteristics 有权
标题翻译：具有改善的响应特性的电容式触摸面板
公开(公告)号：US09128571B2
公开(公告)日：2015-09-08
申请号：US13555556
申请日：2012-07-23
申请人： Nathan Y. Moyal , Tao Peng , Jerry L. Doorenbos , Ronald F. Cormier
发明人： Nathan Y. Moyal , Tao Peng , Jerry L. Doorenbos , Ronald F. Cormier
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0416 , G06F2203/04103 , G06F2203/04111
摘要： An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection electrodes that are spaced apart and electrically isolated from one another and an associated set of interleavers. Each interleaver is located between adjacent detection electrodes from its associated the set of detection electrodes, and each set of interleavers also includes a pair of complementary interleaving electrodes coupled to those that are electrically coupled to the adjacent detection electrodes from its associated set of detection electrodes. The detection electrodes and interleaving electrodes are also substantially transparent to visible spectrum light.
摘要翻译：提供了一种装置。该装置包括设置在第一层上的第二层。第一层和第二层中的每一层具有彼此间隔开并且电隔离的一组检测电极以及相关联的一组交织器。每个交织器位于相邻的检测电极之间，与其相关联的检测电极组相关联，并且每组交织器还包括一对互补交错电极，其耦合到从其相关联的检测电极电耦合到相邻检测电极的那些。检测电极和交错电极对可见光谱光也是基本透明的。

9. 发明授权

US08610484B2 Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method 有权
标题翻译：双极晶体管抗饱和钳使用辅助双极级，和方法
公开(公告)号：US08610484B2
公开(公告)日：2013-12-17
申请号：US12804752
申请日：2010-07-28
申请人： Sudarshan Udayashankar , Jerry L. Doorenbos
发明人： Sudarshan Udayashankar , Jerry L. Doorenbos
IPC分类号： H03K5/08 , H03F3/16
CPC分类号： H03K5/08
摘要： An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
摘要翻译：输出级（1-2）包括用于驱动具有集电极的主晶体管（Q3）的基极的增益电路（Q1，Q2），其响应于输入信号V11而耦合到输出端（18），该输入信号也控制具有耦合到输出的集电极的辅助晶体管（Q7）的基极。钳位晶体管（Q6）具有耦合到辅助晶体管的基极的控制电极，耦合到输出的第一电极和耦合以提供从输出经由增益电路到主晶体管的基极的反馈的第二电极，以及以提供从输出到辅助晶体管的基极的反馈。当辅助晶体管进入深饱和时，使钳位晶体管从输出端向主输出级提供负反馈，以防止主晶体管进入深饱和。

10. 发明申请

US20100019842A1 Low-noise, wide offset range, programmable input offset amplifier front end and method 有权
标题翻译：低噪声，宽偏移范围，可编程输入失调放大器前端和方法
公开(公告)号：US20100019842A1
公开(公告)日：2010-01-28
申请号：US12229278
申请日：2008-08-21
申请人： Tony R. Larson , Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Tony R. Larson , Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03F1/02 , H03G3/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/45928 , H03F3/72 , H03F2203/45101 , H03F2203/45482 , H03F2203/45494 , H03F2203/45616 , H03F2203/45678 , H03F2203/45681
摘要： A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin−) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (−) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
摘要翻译：可编程偏移放大器包括具有与第一（Vin +）和第二（Vin-）输入电压耦合的差分连接的源极和第一（M1）和第二（M2）输入晶体管。尾电流（Itail1）在第一和第二输入晶体管之间共享。第一（M3）和第二（M4）负载装置分别耦合在参考电压和第一和第二输入晶体管的漏极之间。输出级（13）具有耦合到第二输入晶体管的漏极的第一输入（+）和耦合到第一输入晶体管的漏极的第二输入（ - ）。可编程电压变化在可编程输入偏移电路的输入元件上产生，以引起与输入晶体管的电极相关联的偏移电压的变化，其被反射回到放大器输入端以提供大的可编程输入参考偏移电压。

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