专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08984217B2 System and method of reducing power usage of a content addressable memory 有权
标题翻译：减少内容可寻址存储器的功率使用的系统和方法
公开(公告)号：US08984217B2
公开(公告)日：2015-03-17
申请号：US12862277
申请日：2010-08-24
申请人： Jian Shen , Dang D. Hoang , Paul D. Bassett
发明人： Jian Shen , Dang D. Hoang , Paul D. Bassett
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/26 , G06F1/32 , G11C15/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A system is disclosed that includes a content addressable memory and an input register coupled to the content addressable memory. The input register can store a data word and the content addressable memory determines if the data word exists in the content addressable memory. The system also includes a power control circuit coupled to the content addressable memory for selectively providing power to at least a portion of the content addressable memory. The system includes power control logic coupled to the power control circuit to selectively reduce power to the at least a portion of the content addressable memory when valid data does not exist in the at least a portion of the content addressable memory.
摘要翻译：公开了一种包括内容可寻址存储器和耦合到内容可寻址存储器的输入寄存器的系统。输入寄存器可以存储数据字，并且内容可寻址存储器确定数据字是否存在于内容可寻址存储器中。该系统还包括耦合到内容可寻址存储器的功率控制电路，用于选择性地向内容可寻址存储器的至少一部分提供电力。当在内容可寻址存储器的至少一部分中不存在有效数据时，该系统包括耦合到功率控制电路的功率控制逻辑，以选择性地降低内容可寻址存储器的至少一部分的功率。

2. 发明申请

US20120054426A1 System and Method of Reducing Power Usage of a Content Addressable Memory 有权
标题翻译：减少内容可寻址存储器的电源使用的系统和方法
公开(公告)号：US20120054426A1
公开(公告)日：2012-03-01
申请号：US12862277
申请日：2010-08-24
申请人： Jian Shen , Dang D. Hoang , Paul D. Bassett
发明人： Jian Shen , Dang D. Hoang , Paul D. Bassett
IPC分类号： G11C15/00 , G06F12/02 , G11C5/14
CPC分类号： G11C15/04
摘要： A system is disclosed that includes a content addressable memory and an input register coupled to the content addressable memory. The input register can store a data word and the content addressable memory determines if the data word exists in the content addressable memory. The system also includes a power control circuit coupled to the content addressable memory for selectively providing power to at least a portion of the content addressable memory. The system includes power control logic coupled to the power control circuit to selectively reduce power to the at least a portion of the content addressable memory when valid data does not exist in the at least a portion of the content addressable memory.
摘要翻译：公开了一种包括内容可寻址存储器和耦合到内容可寻址存储器的输入寄存器的系统。输入寄存器可以存储数据字，并且内容可寻址存储器确定数据字是否存在于内容可寻址存储器中。该系统还包括耦合到内容可寻址存储器的功率控制电路，用于选择性地向内容可寻址存储器的至少一部分提供电力。当在内容可寻址存储器的至少一部分中不存在有效数据时，该系统包括耦合到功率控制电路的功率控制逻辑，以选择性地降低内容可寻址存储器的至少一部分的功率。

3. 发明申请

US20130076424A1 SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS 审中-公开
标题翻译：减少交叉耦合效应的系统和方法
公开(公告)号：US20130076424A1
公开(公告)日：2013-03-28
申请号：US13242469
申请日：2011-09-23
申请人： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
发明人： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
IPC分类号： H03H11/26
CPC分类号： G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
摘要： A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.
摘要翻译：一种装置包括耦合到多条总线线路的多个驱动电路。多个驱动器电路的第一驱动电路耦合到多条总线的第一总线。第一驱动器电路包括偏置反相器，电平移位器，锁存器和读出放大器之一，其被配置为产生响应于输入信号从高到低的第一数字值转换的第一延迟之后转变的输出信号并且响应于输入信号从低到高的第二数字值转换而在第二延迟之后转变。第一延迟与第二延迟不同，其量足以减少与第一总线线路上的信号的传输相关的功率，并且在与第一总线线路紧密接近的第二总线上。

4. 发明申请

US20110215827A1 Method and Apparatus for Testing a Memory Device 失效
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US20110215827A1
公开(公告)日：2011-09-08
申请号：US12716341
申请日：2010-03-03
申请人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
发明人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译：在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。该偏压由对控制器作出响应的偏置电路提供。当井被偏置时，执行半导体器件的测试以产生测试数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式