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1. 发明授权

US06822497B1 Clock generator 有权
标题翻译：时钟发生器
公开(公告)号：US06822497B1
公开(公告)日：2004-11-23
申请号：US10460959
申请日：2003-06-13
申请人： Jianguo Yao , Matthew Courcy
发明人： Jianguo Yao , Matthew Courcy
IPC分类号： G06F104
CPC分类号： G06F1/04
摘要： A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.
摘要翻译：一种产生时钟的系统和方法。第一个时钟被访问。创建第一个时钟的延迟版本。产生第二个时钟信号。第二时钟信号的第一边缘对应于第一时钟信号的转变，并且第二时钟信号的第二边缘对应于第一时钟信号的延迟版本的转变。

2. 发明授权

US09239457B2 Circuits for controlling display apparatus 有权
标题翻译：用于控制显示装置的电路
公开(公告)号：US09239457B2
公开(公告)日：2016-01-19
申请号：US13548007
申请日：2012-07-12
申请人： Stephen R. Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
发明人： Stephen R. Lewis , Stephen English , Jianguo Yao , John DeRoo , Roger W. Barton
IPC分类号： G02B26/00 , G02F1/03 , G02F1/07 , G02B26/02 , G09G3/34
CPC分类号： G02B26/02 , G02B26/005 , G02B26/023 , G09G3/3433 , G09G3/3466 , G09G2300/0465 , G09G2300/0473 , G09G2300/0838 , G09G2300/0842 , G09G2300/0857 , G09G2300/0866 , G09G2300/0876 , G09G2310/063
摘要： A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.
摘要翻译：显示装置包括光调制器阵列。每个光调制器具有被配置为将光调制器驱动到第一状态的第一致动器和被配置为将光调制器驱动到第二状态的第二致动器。该显示装置还包括一个控制矩阵，对于阵列中的每个光调制器，包括单个致动电压互连。致动电压互连被配置为将第一驱动电压施加到光调制器的第一致动器并将第二驱动电压施加到光调制器的第二致动器。此外，致动电压互连被配置为控制向锁存电路施加数据电压以控制第一和第二驱动电压施加到第一和第二致动器。

3. 发明授权

US07733144B2 Radiation hardened CMOS master latch with redundant clock input circuits and design structure therefor 失效
标题翻译：具有冗余时钟输入电路的辐射硬化CMOS主锁存器及其设计结构
公开(公告)号：US07733144B2
公开(公告)日：2010-06-08
申请号：US12128761
申请日：2008-05-29
申请人： Xi Guo , Jerry P. Liu , Jianguo Yao
发明人： Xi Guo , Jerry P. Liu , Jianguo Yao
IPC分类号： H03K3/289
CPC分类号： H03K3/356139 , H03K3/0375
摘要： A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch.
摘要翻译：用于在GHz频率工作的可编程相分频器中的辐射硬化主锁存器在深亚微米CMOS技术中实现，并且由以DICE类型配置互连的两个相同的半电路组成，使得主锁存器免受单个事件的不适（SEU）影响其四个数据输入中的最多一个。每个半电路包括具有四个子时钟节点的时钟输入电路，每个子时钟节点由反相器耦合到公共时钟输入。时钟输入电路被配置为冗余的，使得主锁存半电路的操作也不受影响至多一个与多个子时钟节点相关联的反相器的SEU。辐射硬化主闩锁位于体现在存储用于设计，制造和/或测试主闩锁的信息的机器可读介质中的设计结构中。

4. 发明授权

US07671779B1 System and method for reducing power consumption in a multi-channel signal processor 有权
标题翻译：用于降低多信道信号处理器功耗的系统和方法
公开(公告)号：US07671779B1
公开(公告)日：2010-03-02
申请号：US11799977
申请日：2007-05-03
申请人： Michael J. Guidry, Jr. , Jianguo Yao , Matthew L. Courcy
发明人： Michael J. Guidry, Jr. , Jianguo Yao , Matthew L. Courcy
IPC分类号： H03M1/12
CPC分类号： H04N5/378 , H03M1/0682 , H03M1/1023 , H03M1/1215 , H03M1/1225 , H03M1/1295
摘要： An analog front end for a multi-channel signal processor is provided. The analog front end includes a first stage that is operable to receive a plurality of channel inputs. The first stage includes a ping/pong capacitor array corresponding to each of the channel inputs and an operational amplifier that may be coupled successively to each of the ping/pong capacitor arrays.
摘要翻译：提供了一种用于多通道信号处理器的模拟前端。模拟前端包括可操作以接收多个通道输入的第一级。第一级包括对应于每个通道输入的乒乓电容阵列和可连续耦合到每个乒乓电容阵列的运算放大器。

5. 发明授权

US09044717B2 Centrifugal device 有权
标题翻译：离心装置
公开(公告)号：US09044717B2
公开(公告)日：2015-06-02
申请号：US13252863
申请日：2011-10-04
申请人： Jianguo Yao
发明人： Jianguo Yao
IPC分类号： B01F9/00 , B01F15/06 , B02C17/08 , B02C17/18
CPC分类号： B01F9/0001 , B01F15/065 , B02C17/08 , B02C17/1815
摘要： A centrifugal device capable of adjusting a temperature of a material. The centrifugal device applies centrifugal force on a contained material contained within a container by spinning the container while rotating the container. The centrifugal device includes: a rotating body rotating around a predetermined rotation axis line; a container holder that holds the container and is attached in a rotatable manner to the rotating body in a position that is a predetermined distance away from the rotation axis line of the rotating body; a compartment body that compartmentalizes a space including an area in which the rotating body rotates; one or a plurality of projection bodies that project from an inner surface of the compartment body towards the area in which the rotating body rotates; and a temperature adjustor that adjusts the temperature of the compartment body.
摘要翻译：能够调节材料温度的离心装置。离心装置通过在旋转容器的同时旋转容器而对包含在容器内的容纳物质施加离心力。离心装置包括：围绕预定旋转轴线旋转的旋转体; 容器保持器，其容纳所述容器，并且以与所述旋转体的旋转轴线成预定距离的位置可旋转地安装在所述旋转体上; 隔间体，其隔开包括旋转体旋转的区域的空间; 一个或多个突起体，其从隔室主体的内表面朝向旋转体旋转的区域突出; 以及调节室体温度的温度调节器。

6. 发明授权

US08686782B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08686782B2
公开(公告)日：2014-04-01
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

7. 发明申请

US20120187987A1 STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：频率自适应电平变换电路的结构
公开(公告)号：US20120187987A1
公开(公告)日：2012-07-26
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L7/08 , H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

8. 发明申请

US20120135846A1 Centrifuge 有权
标题翻译：离心机
公开(公告)号：US20120135846A1
公开(公告)日：2012-05-31
申请号：US13252863
申请日：2011-10-04
申请人： Jianguo Yao
发明人： Jianguo Yao
IPC分类号： B04B15/02
CPC分类号： B01F9/0001 , B01F15/065 , B02C17/08 , B02C17/1815
摘要： The present invention provides a centrifuge capable of adjusting a temperature of a material.The centrifuge is a spinning and revolving type centrifuge that applies centrifugal force on a contained material contained within a container by spinning the container while rotating the container. The centrifuge includes: a rotating body configured to be capable of rotating around a predetermined rotation axis line; a container holder that holds the container and is attached in a rotatable manner to the rotating body in a position that is a predetermined distance away from the rotation axis line of the rotating body; a compartment body that compartmentalizes a space including an area in which the rotating body rotates; one or a plurality of projection bodies that project from an inner surface of the compartment body towards the area in which the rotating body rotates; and a temperature adjustor that adjusts the temperature of the compartment body.
摘要翻译：本发明提供一种能够调节材料的温度的离心机。离心机是一种旋转和旋转式离心机，通过在旋转容器的同时旋转容器，将离心力施加在容纳在容器内的容纳物上。离心机包括：旋转体，构造成能够围绕预定的旋转轴线旋转; 容器保持器，其保持容器并且以与旋转体的旋转轴线预定距离的位置可旋转地附接到旋转体; 隔间体，其隔开包括旋转体旋转的区域的空间; 一个或多个突起体，其从隔室主体的内表面朝向旋转体旋转的区域突出; 以及调节室体温度的温度调节器。

9. 发明申请

US20120133413A1 DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：一种频率自适应电平变换电路的设计结构
公开(公告)号：US20120133413A1
公开(公告)日：2012-05-31
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

10. 发明申请

US20100188126A1 Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation 审中-公开
标题翻译：电压控制占空比和非重叠时钟发生实现
公开(公告)号：US20100188126A1
公开(公告)日：2010-07-29
申请号：US12359583
申请日：2009-01-26
申请人： Sharon W. Cheung , Chad B. McBride , Cheng-Fu Frank Tsai , Jianguo Yao
发明人： Sharon W. Cheung , Chad B. McBride , Cheng-Fu Frank Tsai , Jianguo Yao
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A method, system and apparatus for controlling the duty cycle of a clock to optimize duty cycle correction and non over-lapping clock generation. The first system generates a reference voltage and one or more clock signals. A comparison is made between the DC level of an output clock and the reference voltage. A correct duty cycle of the clock signal is equal to a predetermined ratio of high time to low time, within an acceptable margin, wherein the ratio of high time to low time is derived from a first resistor and a second resistor. A second system is developed to generate non-overlap clock signals with non-overlap gap control, wherein a reference voltage of a first circuit network is the reference voltage of a second circuit network; thereby generating a single reference signal for the non-overlap circuit network.
摘要翻译：用于控制时钟的占空比以优化占空比校正和非重叠时钟生成的方法，系统和装置。第一个系统产生参考电压和一个或多个时钟信号。比较输出时钟的直流电平和参考电压。在可接受的余量内，时钟信号的正确占空比等于高时间到低时间的预定比率，其中从第一电阻器和第二电阻器导出高时间与低电平的比率。开发了第二系统以产生具有非重叠间隙控制的非重叠时钟信号，其中第一电路网络的参考电压是第二电路网络的参考电压; 从而生成用于非重叠电路网络的单个参考信号。

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