专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08135103B1 Mixed domain spread spectrum clocking for use in imaging systems for maximum imaging quality and optimized EMI performance 有权
标题翻译：混合域扩频时钟，用于成像系统，实现最高的成像质量和优化的EMI性能
公开(公告)号：US08135103B1
公开(公告)日：2012-03-13
申请号：US12099666
申请日：2008-04-08
申请人： Matthew Courcy , David Barkin , James Brinkhurst
发明人： Matthew Courcy , David Barkin , James Brinkhurst
IPC分类号： H04L7/00 , H03D3/24 , H03L7/06
CPC分类号： H03L7/197
摘要： A method of operating a line imaging device including receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a second clock signal based on the first clock signal and being unmodulated where the second clock signal being used for driving the imager timing, data sampling and digitizing operations of the line imaging device, and generating a third clock signal based on the first clock signal and being modulated using a spreading waveform where the third clock signal being a spread spectrum clock signal and being used to drive the data transfer operation of the line imaging device.
摘要翻译：一种操作线成像装置的方法，包括：接收在线成像装置中指示系统定时信号的第一时钟信号，基于第一时钟信号产生第二时钟信号，并且在第二时钟信号被用于驱动线性成像装置的成像器定时，数据采样和数字化操作，以及基于第一时钟信号产生第三时钟信号，并使用扩展波形进行调制，其中第三时钟信号是扩频时钟信号，并用于驱动线路成像设备的数据传输操作。

2. 发明授权

US07372391B1 Pipeline ADC with memory effects achieving one cycle absolute over-range recovery 有权
标题翻译：具有记忆效应的管道ADC实现一个周期绝对超范围恢复
公开(公告)号：US07372391B1
公开(公告)日：2008-05-13
申请号：US11677358
申请日：2007-02-21
申请人： Matthew Courcy , Jipeng Li
发明人： Matthew Courcy , Jipeng Li
IPC分类号： H03M1/38
CPC分类号： H03M1/129 , H03M1/0607 , H03M1/0695 , H03M1/1215 , H03M1/44
摘要： A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100) includes an over-range detection and recovery circuit including first and second switches (S3, S4) connected between respective input terminals (136, 137) and output terminals (138, 139) of the opamp (128) and both controlled by a first control signal, and a logic circuit (150) coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.
摘要翻译：一种用于运算放大器共享流水线模数转换器（ADC）（100）的数据转换级电路（104）包括超范围检测和恢复电路，包括连接在各自之间的第一和第二开关（S 3，S 4）输入端子（136,137）和运算放大器（128）的输出端子（138,139），并且均由第一控制信号控制;以及逻辑电路（150），耦合以接收第一残余值并比较第一残留值达到一对高低比较电压电平。当第一个残余值大于高比较电压电平或小于低比较电压电平时，逻辑电路在第一时钟相位期间断言第一控制信号。高和低比较电压电平定义了数据转换级电路的参考电压范围之外的电压区域，其中参考电压范围限定数据转换级电路的范围内的电压值。

3. 发明授权

US07724043B1 Common mode controller for a sample-and-hold circuit 有权
标题翻译：用于采样和保持电路的共模控制器
公开(公告)号：US07724043B1
公开(公告)日：2010-05-25
申请号：US11775745
申请日：2007-07-10
申请人： Robert J. LeBoeuf, II , Matthew Courcy
发明人： Robert J. LeBoeuf, II , Matthew Courcy
IPC分类号： H03K5/00
CPC分类号： G11C27/026
摘要： A common mode controller circuit (60) for maintaining a common mode voltage (Vcm) at a first node (52) and a second node (54) in a sample-and-hold circuit receiving a pair of AC coupled differential input signals (Vinp, Vinn) includes first and second resistors (R1/R2) and third and fourth resistors (R3/R4), each set of resistors connected in series between the first and second nodes, and a differential amplifier (A1) having an inverting input terminal coupled to a third node (62) between the first and second resistors, a non-inverting input terminal coupled to a reference voltage (Vref) and an output terminal coupled to a fourth node (64) between the third and fourth resistors. The common mode voltage is sampled at the third node and the differential amplifier provides a sourcing output current indicative of the difference between the sampled common mode voltage and the reference voltage to drive the fourth node.
摘要翻译：一种用于在接收一对AC耦合差分输入信号（Vinp）的采样和保持电路中的第一节点（52）和第二节点（54）处保持共模电压（Vcm）的共模控制器电路（60），Vinn）包括第一和第二电阻器（R1 / R2）和第三和第四电阻器（R3 / R4），串联连接在第一和第二节点之间的每组电阻器和具有反相输入端子的差分放大器（A1）耦合到第一和第二电阻器之间的第三节点（62），耦合到参考电压（Vref）的非反相输入端子和耦合到第三和第四电阻器之间的第四节点（64）的输出端子。在第三节点对共模电压进行采样，差分放大器提供指示采样的共模电压和参考电压之间的差异的源极输出电流以驱动第四节点。

4. 发明授权

US08160117B1 Line rate spread spectrum clock generator for use in line imaging systems 有权
标题翻译：线速扩频时钟发生器用于线路成像系统
公开(公告)号：US08160117B1
公开(公告)日：2012-04-17
申请号：US12099672
申请日：2008-04-08
申请人： Matthew Courcy
发明人： Matthew Courcy
IPC分类号： H04B1/69 , H04L7/00 , H03D3/24 , H03L7/06
CPC分类号： H04B15/02 , G09G5/18 , G09G2330/06 , H03L7/1974 , H04B1/69 , H04B2215/067 , H04N5/3692 , H04N5/372 , H04N5/3765
摘要： A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading waveform having a frequency as a function of the line length value and having a total number of clock cycles matching the line length value, and modulating the first clock signal using said spreading waveform to generate the spread spectrum clock signal where the spread spectrum clock signal is used for driving the imaging, data sampling and digitizing, and data transfer operation of the line imaging device. The spread spectrum clock has the same clock frequency variation for each scan line of the line imaging device.
摘要翻译：一种生成用于线成像装置的扩频时钟信号的方法，包括接收线成像装置的线长度值，接收在线成像装置中指示系统定时信号的第一时钟信号，产生具有频率的扩频波形作为线长度值的函数，并且具有与线长度值匹配的时钟周期的总数，并且使用所述扩展波形来调制第一时钟信号，以产生扩频时钟信号，其中扩频时钟信号用于驱动成像，数据采样和数字化，以及线路成像设备的数据传输操作。扩频时钟对于行成像装置的每个扫描线具有相同的时钟频率变化。

5. 发明授权

US07345530B1 Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing 有权
标题翻译：具有运算放大器共享的开关电容放大器的调节开关驱动方案
公开(公告)号：US07345530B1
公开(公告)日：2008-03-18
申请号：US11421716
申请日：2006-06-01
申请人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
发明人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.
摘要翻译：包括用于对一对输入信号进行采样的第一和第二对采样电容器的开关电容放大器电路包括耦合以接收第一参考电压并产生与第一参考电压有关的第一调节输出电压的电压调节器，并且独立于第一电源电压; 产生参考第一电源电压的第一和第二时钟信号的时钟信号发生器和参考第一调节输出电压的第三和第四时钟信号; 以及将采样电容器的底板耦合到放大器的第一组开关，第一组开关由第三和第四时钟信号控制。电路还可以包括将采样电容器的顶板耦合到输入信号的第二组开关，第二组开关由第一和第二时钟信号控制。

6. 发明授权

US06822497B1 Clock generator 有权
标题翻译：时钟发生器
公开(公告)号：US06822497B1
公开(公告)日：2004-11-23
申请号：US10460959
申请日：2003-06-13
申请人： Jianguo Yao , Matthew Courcy
发明人： Jianguo Yao , Matthew Courcy
IPC分类号： G06F104
CPC分类号： G06F1/04
摘要： A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.
摘要翻译：一种产生时钟的系统和方法。第一个时钟被访问。创建第一个时钟的延迟版本。产生第二个时钟信号。第二时钟信号的第一边缘对应于第一时钟信号的转变，并且第二时钟信号的第二边缘对应于第一时钟信号的延迟版本的转变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式