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1. 发明授权

US08901680B2 Graphene pressure sensors 有权
标题翻译：石墨烯压力传感器
公开(公告)号：US08901680B2
公开(公告)日：2014-12-02
申请号：US13445029
申请日：2012-04-12
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/06
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在形成于半导体衬底中的空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

2. 发明授权

US08852985B2 Graphene pressure sensors 有权
标题翻译：石墨烯压力传感器
公开(公告)号：US08852985B2
公开(公告)日：2014-10-07
申请号：US13600469
申请日：2012-08-31
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L21/00 , H01L29/02
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在半导体衬底中形成的开放空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

3. 发明申请

US20130273682A1 GRAPHENE PRESSURE SENSORS 有权
标题翻译：石墨压力传感器
公开(公告)号：US20130273682A1
公开(公告)日：2013-10-17
申请号：US13600469
申请日：2012-08-31
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/02
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在半导体衬底中形成的开放空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

4. 发明申请

US20130270511A1 GRAPHENE PRESSURE SENSORS 有权
标题翻译：石墨压力传感器
公开(公告)号：US20130270511A1
公开(公告)日：2013-10-17
申请号：US13445029
申请日：2012-04-12
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/06 , H01L21/02 , B82Y40/00
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在形成于半导体衬底中的空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

5. 发明授权

US09040929B2 Charge sensors using inverted lateral bipolar junction transistors 有权
标题翻译：使用反向横向双极结型晶体管的充电传感器
公开(公告)号：US09040929B2
公开(公告)日：2015-05-26
申请号：US13561671
申请日：2012-07-30
申请人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
发明人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号： G01T1/24 , H01L31/115 , H01L27/146
CPC分类号： G01T1/247 , G01N27/403 , G01T3/08 , H01L27/14 , H01L27/14681 , H01L31/022408 , H01L31/035272 , H01L31/1105 , H01L31/115 , H01L31/118
摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
摘要翻译：传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

6. 发明授权

US08980667B2 Charge sensors using inverted lateral bipolar junction transistors 有权
标题翻译：使用反向横向双极结型晶体管的充电传感器
公开(公告)号：US08980667B2
公开(公告)日：2015-03-17
申请号：US13566324
申请日：2012-08-03
申请人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
发明人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号： H01L31/101 , H01L31/11 , H01L27/14
CPC分类号： G01T1/247 , G01N27/403 , G01T3/08 , H01L27/14 , H01L27/14681 , H01L31/022408 , H01L31/035272 , H01L31/1105 , H01L31/115 , H01L31/118
摘要： A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
摘要翻译：形成传感器的方法包括形成与基底基板接触的基底区域屏障。基区域屏障包括具有与基底衬底相同的掺杂剂导电性的单晶半导体。发射极和集电极形成为与基极区势垒接触并在相对侧上形成双极结型晶体管。集电极，发射极和基极区势垒被平坦化以形成与基底衬底相对的电平表面，使得当电平表面暴露于电荷时，在双极结型晶体管的操作期间测量电荷。

7. 发明申请

US20140030838A1 CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS 有权
标题翻译：充电传感器使用反转的双极双极晶体管
公开(公告)号：US20140030838A1
公开(公告)日：2014-01-30
申请号：US13566324
申请日：2012-08-03
申请人： Jin Cai , Tak H Ning , Jeng-Bang Yau , Sufi Zafar
发明人： Jin Cai , Tak H Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号： H01L21/02
CPC分类号： G01T1/247 , G01N27/403 , G01T3/08 , H01L27/14 , H01L27/14681 , H01L31/022408 , H01L31/035272 , H01L31/1105 , H01L31/115 , H01L31/118
摘要： A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
摘要翻译：形成传感器的方法包括形成与基底基板接触的基底区域屏障。基区域屏障包括具有与基底衬底相同的掺杂剂导电性的单晶半导体。发射极和集电极形成为与基极区势垒接触并在相对侧上形成双极结型晶体管。集电极，发射极和基极区势垒被平坦化以形成与基底衬底相对的电平表面，使得当电平表面暴露于电荷时，在双极结型晶体管的操作期间测量电荷。

8. 发明授权

US08541835B2 Schottky FET fabricated with gate last process 有权
标题翻译：用最后一道工艺制造的肖特基FET
公开(公告)号：US08541835B2
公开(公告)日：2013-09-24
申请号：US13571429
申请日：2012-08-10
申请人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
发明人： Jin Cai , Dechao Guo , Marwan H. Khater , Christian Lavoie , Zhen Zhang
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66621
摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.
摘要翻译：场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

9. 发明授权

US08492794B2 Vertical polysilicon-germanium heterojunction bipolar transistor 有权
公开(公告)号：US08492794B2
公开(公告)日：2013-07-23
申请号：US13048366
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

10. 发明申请

US20130005095A1 ETSOI CMOS With Back Gates 有权
标题翻译： ETSOI CMOS后盖
公开(公告)号：US20130005095A1
公开(公告)日：2013-01-03
申请号：US13611656
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203
摘要： A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
摘要翻译：制造结构的方法包括提供绝缘体上硅晶片，通过半导体层和绝缘层注入具有与衬底顶表面相邻的第一导电类型的功能区域; 在功能区域内通过半导体层和绝缘层注入具有第二类导电性的电浮置背栅区; 在半导体层中形成隔离区; 形成第一和第二晶体管器件以在半导体层上具有相同类型的导电性，使得晶体管器件中的一个覆盖在注入的背栅极区域上，另一个晶体管器件仅覆盖不重叠的功能区域的下面的顶部表面通过植入的背栅区; 以及向所述功能区域提供电接触以施加偏置电压。

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