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    • 5. 发明申请
    • Method for Manufacturing Gate of Non Volatile Memory Device
    • 非易失性存储器件栅极制造方法
    • US20080064195A1
    • 2008-03-13
    • US11750059
    • 2007-05-17
    • Young-Ju Kim
    • Young-Ju Kim
    • H01L21/3205
    • H01L29/7885H01L21/31116H01L21/32137H01L29/40114H01L29/7883
    • A method for manufacturing the gate of the non-volatile memory device is characterized in in-situ etching a tungsten silicide film, polycrystalline silicon films, an ONO film, and a silicon oxide film with one step using one etchant having a lower etch selectivity on the silicon and oxide films in order to form the gate. As such, in-situ etching the material films for forming the gate with one step using an etchant having a low etch selectivity on the silicon and oxide films can prevent undercuts from occurring on an interface between two different material films to thereby improve cell distribution, minimize the occurrence of particles, and reduce processing time over a prior art.
    • 一种用于制造非易失性存储器件的栅极的方法的特征在于,使用具有较低蚀刻选择性的一种蚀刻剂以一步法原位蚀刻硅化钨膜,多晶硅膜,ONO膜和氧化硅膜 硅和氧化膜以形成栅极。 因此,使用在硅和氧化物膜上具有低蚀刻选择性的蚀刻剂以一步法原位蚀刻用于形成栅极的材料膜可以防止在两种不同材料膜之间的界面上发生底切,从而改善电池分布, 最小化颗粒的发生,并减少处理时间超过现有技术。
    • 7. 发明授权
    • Test point structure for RF calibration and test of printed circuit board and method thereof
    • 射频校准和印刷电路板测试的测试点结构及其方法
    • US08581606B2
    • 2013-11-12
    • US12622677
    • 2009-11-20
    • Young-Ju Kim
    • Young-Ju Kim
    • G01R31/00
    • G01R31/2818G01R31/2822G01R35/005H05K1/0237H05K1/0268H05K2201/10098
    • A point structure for RF calibration and testing of a PCB is provided. The point structure includes a test pad, an antenna connection pad, and a device mounting pad. The test pad is connected to a circuit unit of the PCB, and a ground pad is connected with a ground of the PCB. A contact probe apparatus for performing RF calibration and testing is connected to the test pad and the ground pad. The antenna connection pad is connected to an antenna unit. The device mounting pad is connected with the test pad and the antenna connection pad. An antenna device is mounted on the device mounting pad. The test pad, the ground pad, the antenna connection pad, and the device mounting pad are separated from one another. Since the point structure can replace an RF switch, a circuit area on the PCB may be reduced, a mounting space may be secured, and a manufacturing cost may be reduced.
    • 提供了用于RF校准和PCB测试的点结构。 点结构包括测试垫,天线连接垫和装置安装垫。 测试焊盘连接到PCB的电路单元,接地焊盘与PCB的接地连接。 用于进行RF校准和测试的接触探针装置连接到测试垫和接地垫。 天线连接垫连接到天线单元。 设备安装垫与测试垫和天线连接垫连接。 天线装置安装在设备安装垫上。 测试垫,接地垫,天线连接垫和设备安装垫彼此分离。 由于点结构可以替代RF开关,所以可以减小PCB上的电路区域,可以确保安装空间,并且可以降低制造成本。
    • 8. 发明授权
    • Filter circuit and integrated circuit including the same
    • 滤波电路和集成电路包括相同
    • US08461916B2
    • 2013-06-11
    • US12981161
    • 2010-12-29
    • Hae-Rang ChoiYoung-Ju Kim
    • Hae-Rang ChoiYoung-Ju Kim
    • H03K5/00
    • G11C19/287H03H17/026H03H17/0283
    • A filter circuit includes a plurality of shifting units configured to each store an initial value, receive at least one input signal, and shift the stored value to a next shifting unit in sequence from among the shifting units in response to at least one input signal, and an initial value setting unit configured to set the initial stored values of the shifting units to different sets of initial stored values in response to different filter setting signals, respectively, wherein the different filter setting signals represent respectively different criteria for filtering the at least one input signal, wherein the initially stored values have a first logic value or a second logic value, wherein the filter circuit is configured to activate an output signal when the first logic value is shifted to a selected shifting unit among the plurality of shifting units.
    • 滤波器电路包括多个移位单元,每个移位单元被配置为每个存储初始值,接收至少一个输入信号,并且响应于至少一个输入信号,从移位单元中顺序地将存储的值移位到下一个移位单元, 以及初始值设定单元,被配置为分别响应于不同的滤波器设置信号将移位单元的初始存储值设置为不同的初始存储值集合,其中不同的滤波器设置信号分别表示用于过滤至少一个 输入信号,其中所述初始存储的值具有第一逻辑值或第二逻辑值,其中所述滤波器电路被配置为当所述多个移位单元中的所述第一逻辑值移位到所选择的移位单元时激活输出信号。
    • 10. 发明授权
    • Semiconductor integrated circuit and semiconductor package module having the same
    • 具有相同的半导体集成电路和半导体封装模块
    • US07791396B2
    • 2010-09-07
    • US11822268
    • 2007-07-03
    • Young-Ju KimKwan-Weon Kim
    • Young-Ju KimKwan-Weon Kim
    • H03L5/00
    • H03K19/0016
    • A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.
    • 半导体集成电路包括:第一时钟引脚控制器,其接收反射镜功能信号和测试模式信号,以响应正常模式下的镜像功能信号产生第一输入缓冲器控制信号。 第二时钟引脚控制器响应于正常模式下的镜像功能信号,接收镜像功能信号和测试模式信号,以产生作为第一输入缓冲器控制信号的反相信号的第二输入缓冲器控制信号。 输入缓冲单元分别响应于第一输入缓冲器控制信号和第二输入缓冲器控制信号产生第一和第二引脚的输出信号。