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1. 发明授权

US08633762B2 Integrated circuit chip and transmitting /receiving system including the same 有权
标题翻译：集成电路芯片和发送/接收系统包括相同的
公开(公告)号：US08633762B2
公开(公告)日：2014-01-21
申请号：US13333692
申请日：2011-12-21
申请人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
发明人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC分类号： H01L25/00
CPC分类号： G06F13/4077
摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.
摘要翻译：用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作数据线的线和阵列信息，以防止在数据线中发生串扰。

2. 发明授权

US08625734B2 Counting circuit of semiconductor device and duty correction circuit of semiconductor device using the same 有权
标题翻译：半导体器件的计数电路和使用其的半导体器件的占空比校正电路
公开(公告)号：US08625734B2
公开(公告)日：2014-01-07
申请号：US13366425
申请日：2012-02-06
申请人： Hae-Rang Choi , Yong-Ju Kim
发明人： Hae-Rang Choi , Yong-Ju Kim
IPC分类号： H03K21/00
CPC分类号： H03K5/1565 , H03K21/38
摘要： A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
摘要翻译：半导体器件的计数电路包括多个计数单元，其被配置为分别响应于多个计数时钟对计数代码的各个位进行计数，并且响应于计数控制信号而在计数方向上进行控制; 时钟切换控制单元，被配置为响应于时钟控制信号来控制在多个计数时钟之间切换的计数时钟的数量; 以及计数操作控制单元，被配置为比较目标代码的值和计数代码的值，并且根据比较结果确定计数控制信号的值。

3. 发明申请

US20130041612A1 INTERNAL CONTROL SIGNAL REGURATION CIRCUIT 有权
标题翻译：内部控制信号恢复电路
公开(公告)号：US20130041612A1
公开(公告)日：2013-02-14
申请号：US13341682
申请日：2011-12-30
申请人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
发明人： Yong Ju Kim , Dae Han Kwon , Hae Rang Choi , Jae Min Jang
IPC分类号： G06F19/00
CPC分类号： G05B19/042 , G05B2219/23314 , G05B2219/24036 , G05B2219/24037
摘要： An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.
摘要翻译：内部控制信号调节电路包括：编程测试单元，被配置为响应于外部控制信号检测内部控制信号，并产生选择信号，测试代码和编程使能信号; 以及代码处理单元，被配置为响应于所述选择信号接收所述测试代码或编程代码并调节所述内部控制信号。

4. 发明申请

US20130033294A1 COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：使用其的半导体器件的半导体器件的计数电路和占空比校正电路
公开(公告)号：US20130033294A1
公开(公告)日：2013-02-07
申请号：US13366425
申请日：2012-02-06
申请人： Hae-Rang CHOI , Yong-Ju Kim
发明人： Hae-Rang CHOI , Yong-Ju Kim
IPC分类号： H03K3/017 , H03K23/00
CPC分类号： H03K5/1565 , H03K21/38
摘要： A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
摘要翻译：半导体器件的计数电路包括多个计数单元，其被配置为分别响应于多个计数时钟对计数代码的各个位进行计数，并且响应于计数控制信号而在计数方向上进行控制; 时钟切换控制单元，被配置为响应于时钟控制信号来控制在多个计数时钟之间切换的计数时钟的数量; 以及计数操作控制单元，被配置为比较目标代码的值和计数代码的值，并且根据比较结果确定计数控制信号的值。

5. 发明授权

US08339159B2 Input buffer circuit of semiconductor apparatus 有权
标题翻译：半导体装置的输入缓冲电路
公开(公告)号：US08339159B2
公开(公告)日：2012-12-25
申请号：US12540496
申请日：2009-08-13
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

6. 发明申请

US20120112824A1 FILTER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：滤波电路和集成电路，包括它们
公开(公告)号：US20120112824A1
公开(公告)日：2012-05-10
申请号：US12981161
申请日：2010-12-29
申请人： Hae-Rang CHOI , Young-Ju Kim
发明人： Hae-Rang CHOI , Young-Ju Kim
IPC分类号： H03K5/00
CPC分类号： G11C19/287 , H03H17/026 , H03H17/0283
摘要： A filter circuit includes a plurality of shifting units configured to each store an initial value, receive at least one input signal, and shift the stored value to a next shifting unit in sequence from among the shifting units in response to at least one input signal, and an initial value setting unit configured to set the initial stored values of the shifting units to different sets of initial stored values in response to different filter setting signals, respectively, wherein the different filter setting signals represent respectively different criteria for filtering the at least one input signal, wherein the initially stored values have a first logic value or a second logic value, wherein the filter circuit is configured to activate an output signal when the first logic value is shifted to a selected shifting unit among the plurality of shifting units.
摘要翻译：滤波器电路包括多个移位单元，每个移位单元被配置为每个存储初始值，接收至少一个输入信号，并且响应于至少一个输入信号，从移位单元中顺序地将存储的值移位到下一个移位单元，以及初始值设定单元，被配置为分别响应于不同的滤波器设置信号将移位单元的初始存储值设置为不同的初始存储值集合，其中不同的滤波器设置信号分别表示用于过滤至少一个输入信号，其中所述初始存储的值具有第一逻辑值或第二逻辑值，其中所述滤波器电路被配置为当所述多个移位单元中的所述第一逻辑值移位到所选择的移位单元时激活输出信号。

7. 发明申请

US20110267124A1 CLOCK SIGNAL DUTY CORRECTION CIRCUIT 有权
标题翻译：时钟信号校正电路
公开(公告)号：US20110267124A1
公开(公告)日：2011-11-03
申请号：US12846669
申请日：2010-07-29
申请人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要翻译：时钟信号占空比校正电路包括：第一转移定时控制单元，被配置为通过使用时钟信号产生用于控制占空比校正时钟信号的上升定时的第一控制信号; 第二转移定时控制单元，被配置为通过使用根据代码信号的时钟信号来生成用于改变占空比校正时钟信号的下降定时的第二控制信号; 以及差分缓冲器单元，被配置为响应于所述第一控制信号和所述第二控制信号而生成其上升时间或下降时间被调整的占空比校正时钟信号。

8. 发明授权

US08026701B2 Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
标题翻译：用于同步时钟系统的电压调节器，以减少时钟树抖动
公开(公告)号：US08026701B2
公开(公告)日：2011-09-27
申请号：US12265908
申请日：2008-11-06
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/652
CPC分类号： G11C5/147
摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.
摘要翻译：具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。电压产生单元基于参考电压产生调节电压。微调电容器单元控制电压产生单元的负载电容。第二缓冲链使用调节电压作为电源电压来延迟时钟信号。控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

9. 发明授权

US08018265B1 Differential signal generation circuit 有权
标题翻译：差分信号发生电路
公开(公告)号：US08018265B1
公开(公告)日：2011-09-13
申请号：US12840255
申请日：2010-07-20
申请人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Yong Ju Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： H03K5/13
CPC分类号： H03K5/1515
摘要： A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.
摘要翻译：差分信号发生电路包括：逆变器阵列，被配置为顺序地反转输入信号以产生多个延迟信号; 以及相位混合器，被配置为以预设的混合比混合多个延迟信号中的第一延迟信号的相位和第二延迟信号的相位，以产生第一差分信号。第一延迟信号具有来自输入信号的第一延迟，并且第二延迟信号具有来自输入信号的第二延迟。差分信号生成电路被配置为从与第一和第二延迟的介质相对应的输入信号产生具有第三延迟的第三延迟信号，并且第三延迟信号被进一步延迟以产生第二差分信号。

10. 发明授权

US07884659B2 Phase mixer and delay locked loop including the same 有权
标题翻译：相位混合器和延迟锁定环包括相同
公开(公告)号：US07884659B2
公开(公告)日：2011-02-08
申请号：US12347298
申请日：2008-12-31
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K11/16
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03L7/0818
摘要： A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.
摘要翻译：相位混合器包括：相位混合单元，被配置为响应于相位控制信号混合第一输入信号的相位和第二输入信号的相位，并输出相位混合信号，该相位混合信号的相位由一个或多个单位单位相位值，以及相位值调整单元，被配置为控制短语混合单元的操作，使得响应于代码信号来编码单位相位值，编码信号编码处理，电压或温度（PVT）变化中的至少一个。

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