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1. 发明申请

US20080205173A1 Method and System for Testing an Integrated Circuit 失效
标题翻译：集成电路测试方法和系统
公开(公告)号：US20080205173A1
公开(公告)日：2008-08-28
申请号：US12022422
申请日：2008-01-30
申请人： Joerg Kliewer , Klaus Nierle , Martin Versen
发明人： Joerg Kliewer , Klaus Nierle , Martin Versen
IPC分类号： G01R31/02 , G01R31/3187 , G11C29/00
CPC分类号： G01R31/3004
摘要： An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.
摘要翻译：一种集成电路，包括：a）至少一个集成电压发生器，用于为相关联的集成负载产生低电压; b）连接到所述电压发生器的集成电压发生器测试逻辑，所述电压发生器在作为所述集成电压发生器的操作状态的测试操作模式中，所述电压发生器测试逻辑根据外部控制信号而在有效工作状态和待机操作状态 c）用于将所述产生的负载电压切换到所述集成负载的内部负载开关，所述内部负载开关可通过内部控制信号来控制; d）其中所述测试操作模式中的所述电压发生器测试逻辑独立于相关联的内部控制切换信号切换所述集成电压发生器的操作状态，以设置施加到该负载的所述负载电压的时间电压分布。

2. 发明授权

US07729186B2 Method and system for testing an integrated circuit 失效
标题翻译：用于测试集成电路的方法和系统
公开(公告)号：US07729186B2
公开(公告)日：2010-06-01
申请号：US12022422
申请日：2008-01-30
申请人： Joerg Kliewer , Klaus Nierle , Martin Versen
发明人： Joerg Kliewer , Klaus Nierle , Martin Versen
IPC分类号： G11C7/00
CPC分类号： G01R31/3004
摘要： An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.
摘要翻译：一种集成电路，包括：a）至少一个集成电压发生器，用于为相关联的集成负载产生低电压; b）连接到所述电压发生器的集成电压发生器测试逻辑，所述电压发生器在作为所述集成电压发生器的操作状态的测试操作模式中，所述电压发生器测试逻辑根据外部控制信号而在有效工作状态和待机操作状态 c）用于将所述产生的负载电压切换到所述集成负载的内部负载开关，所述内部负载开关可通过内部控制信号来控制; d）其中所述测试操作模式中的所述电压发生器测试逻辑独立于相关联的内部控制切换信号切换所述集成电压发生器的操作状态，以设置施加到该负载的所述负载电压的时间电压分布。

3. 发明授权

US07339841B2 Test mode method and apparatus for internal memory timing signals 有权
标题翻译：用于内部存储器定时信号的测试模式方法和装置
公开(公告)号：US07339841B2
公开(公告)日：2008-03-04
申请号：US11227099
申请日：2005-09-16
申请人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
发明人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C29/12015 , G11C29/14 , G11C29/50012
摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.
摘要翻译：测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

4. 发明申请

US20070064505A1 Test mode method and apparatus for internal memory timing signals 有权
标题翻译：用于内部存储器定时信号的测试模式方法和装置
公开(公告)号：US20070064505A1
公开(公告)日：2007-03-22
申请号：US11227099
申请日：2005-09-16
申请人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
发明人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C29/12015 , G11C29/14 , G11C29/50012
摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.
摘要翻译：测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

5. 发明申请

US20060048022A1 Method for testing the serviceability of bit lines in a DRAM memory device 有权
公开(公告)号：US20060048022A1
公开(公告)日：2006-03-02
申请号：US10930132
申请日：2004-08-31
申请人： Martin Versen , Klaus Nierle
发明人： Martin Versen , Klaus Nierle
IPC分类号： G11C29/00
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025
摘要： DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense amplifiers and to the pre-charge circuits (15) subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits (15).

6. 发明授权

US07263019B2 Serial presence detect functionality on memory component 有权
公开(公告)号：US07263019B2
公开(公告)日：2007-08-28
申请号：US11227585
申请日：2005-09-15
申请人： Klaus Nierle , Martin Versen
发明人： Klaus Nierle , Martin Versen
IPC分类号： G11C7/00
CPC分类号： G11C5/04 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611
摘要： Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

7. 发明申请

US20070038804A1 Testmode and test method for increased stress duty cycles during burn in 审中-公开
标题翻译：测试模式和测试方法，用于增加烧伤过程中的应力占空比
公开(公告)号：US20070038804A1
公开(公告)日：2007-02-15
申请号：US11203338
申请日：2005-08-12
申请人： Klaus Nierle , Martin Versen
发明人： Klaus Nierle , Martin Versen
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Embodiments of the invention provide a method, apparatus, and system for operating a memory device. In one embodiment, an inverted refresh command is received. In response to receiving the inverted refresh command, an all bank precharge command is issued. After the all bank precharge command is issued, an all bank activate command is issued, causing wordlines identified by a row address counter to be activated. The identified wordlines are maintained in activated state until a subsequent inverted refresh command is received.
摘要翻译：本发明的实施例提供了一种用于操作存储器件的方法，装置和系统。在一个实施例中，接收到反相刷新命令。响应于接收到反相刷新命令，发出全班预充电命令。在所有银行预充电命令发出之后，发出全部银行激活命令，使得由行地址计数器识别的字线被激活。所识别的字线保持在激活状态，直到接收到后续的反相刷新命令。

8. 发明申请

US20070058470A1 Serial presence detect functionality on memory component 有权
标题翻译：存储器组件上的串行存在检测功能
公开(公告)号：US20070058470A1
公开(公告)日：2007-03-15
申请号：US11227585
申请日：2005-09-15
申请人： Klaus Nierle , Martin Versen
发明人： Klaus Nierle , Martin Versen
IPC分类号： G11C7/00
CPC分类号： G11C5/04 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611
摘要： Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.
摘要翻译：提供了访问串行存在检测数据的方法和装置。对于一些实施例，将串行存在检测逻辑并入存储器件中，从而消除对单独的串行存在检测组件的需要。

9. 发明授权

US07120070B2 Method for testing the serviceability of bit lines in a DRAM memory device 有权
标题翻译：用于测试DRAM存储器件中位线的可用性的方法
公开(公告)号：US07120070B2
公开(公告)日：2006-10-10
申请号：US10930132
申请日：2004-08-31
申请人： Martin Versen , Klaus Nierle
发明人： Martin Versen , Klaus Nierle
IPC分类号： G11C7/00
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025
摘要： DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense amplifiers and to the pre-charge circuits (15) subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits (15).
摘要翻译： DRAM存储器件（1）包括至少一个存储器单元阵列（2,3,4,5），每个存储器单元（12）连接到位线（BL）和字线（WL），每个所述存储器单元位线（BL）连接到读出放大器和预充电电路（15）; 一个可控有功电流发生器（7,8,9,10），用于在读或写访问命令的时间限制的时间间隔内向读出放大器和预充电电路（15）提供功率被施加到DRAM存储器件（1）和分配的切换时间; 用于在切换时间之后向读出放大器和预充电电路（15）提供电力的可控待机电流发生器（6）; 用于接收外部数据，地址和控制信号（C，A，D）并用于控制有功电流发生器（7,8,9,10）和待机电流发生器（6）的控制电路（11）。其中所述控制电路（11）适于控制用于将各个发电机（6,7,8,9,10）切换到所述读出放大器和经受外部测试模式的所述预充电电路（15）的时间用于在测试位线（BL），读出放大器和预充电电路（15）的可用性的测试中减少总体测试时间的信号。

10. 发明申请

US20100306605A1 Apparatus and Method for Manufacturing a Multiple-Chip Memory Device 有权
标题翻译：用于制造多芯片存储器件的装置和方法
公开(公告)号：US20100306605A1
公开(公告)日：2010-12-02
申请号：US12856225
申请日：2010-08-13
申请人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
发明人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/802 , G11C5/04 , G11C2029/4402 , G11C2029/5606
摘要： A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.
摘要翻译：一种用于制造多芯片存储器件的方法包括在半导体衬底上制造易失性存储器元件，检查易失性存储元件的一个或多个初始误差，校正半导体衬底上的一个或多个初始误差，并结合易失性存储元件进入多芯片存储器件，并将非易失性存储器元件结合到多芯片存储器件中。在将易失性存储器元件和非易失性存储器元件并入到多芯片存储器件中之后，检查易失性存储元件中的一个或多个次级错误。修复信息存储在非易失性存储器元件中，修复信息识别一个或多个次要错误。

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