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1. 发明授权

US5995988A Configurable parallel and bit serial load apparatus 有权
标题翻译：可配置并行和位串行负载设备
公开(公告)号：US5995988A
公开(公告)日：1999-11-30
申请号：US131536
申请日：1998-08-10
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.
摘要翻译：一种用于将配置信息加载到可编程集成电路（例如，FPGA）中的装置，可配置为在同一架构内执行并行加载或位串行加载。配置信息在每个N个串行位的数据帧中呈现给FPGA。每个数据帧被分成具有每个Y位的离散串行部分（例如，数据帧包括N / Y部分）。在并行模式下，这些部分被加载到分段配置寄存器中，每个编程周期一个部分，使得Y位并行加载到分段配置寄存器中。在并行加载期间的每个编程时钟周期，数据帧部分的所有位同时加载到配置寄存器的段（每个段的第一位位置），使得每个段在每个编程周期接收一位。然后将配置寄存器的位向下移一个，并为下一个数据帧部分重复循环。在这种机制下，Y位被并行加载到配置寄存器中，以提高传输速率。新型配置寄存器的架构使得其可以以串行模式配置以接收N位数据帧的单个串行比特流，用于向下兼容。

2. 发明授权

US5961576A Configurable parallel and bit serial load apparatus 有权
公开(公告)号：US5961576A
公开(公告)日：1999-10-05
申请号：US176626
申请日：1998-10-22
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

3. 发明授权

US5694056A Fast pipeline frame full detector 失效
标题翻译：快速管线框架全检测器
公开(公告)号：US5694056A
公开(公告)日：1997-12-02
申请号：US627815
申请日：1996-04-01
申请人： John E. Mahoney , Stephen M. Trimberger , Charles R. Erickson
发明人： John E. Mahoney , Stephen M. Trimberger , Charles R. Erickson
IPC分类号： H03K19/177
CPC分类号： H03K19/17704
摘要： A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration data into the IC. Therefore, the present invention advantageously reduces this limiting factor.
摘要翻译：一条流水线全检测电路。本发明可以在使用串行数据流和传送机制将配置数据加载到集成电路（IC）的系统中操作。对于给定的IC，配置数据以指定大小的连续帧传送到IC。配置数据的第一位包含一个帧完整指示符。配置数据被传送到移位寄存器电路中，并且除了存储在移位寄存器电路之外，移位寄存器电路的最后位位置沿特殊帧完整流水线移动到控制单元。控制单元在检测到帧全指示符时，断言并行写入命令，使得移位寄存器电路的数据被并行地传送到存储器的接收列。复位信号后，新的配置数据可以被串行移位到相同的移位寄存器电路中。通过将帧满指示符移动通过流水线，帧全指示器到达控制单元所需的传播延迟显着降低。正是这种传播延迟将配置数据的传输速率限制在IC中。因此，本发明有利地减少了这个限制因素。

4. 发明授权

US5844829A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5844829A
公开(公告)日：1998-12-01
申请号：US985392
申请日：1997-12-04
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

5. 发明授权

US5742531A Configurable parallel and bit serial load apparatus 失效
公开(公告)号：US5742531A
公开(公告)日：1998-04-21
申请号：US642758
申请日：1996-05-03
申请人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
发明人： Philip M. Freidin , Stephen M. Trimberger , John E. Mahoney , Charles R. Erickson
IPC分类号： H03K19/173 , H03K19/177 , G06F1/04 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/1736 , H03K19/17748
摘要： An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

6. 发明授权

US5712579A Deskewed clock distribution network with edge clock 失效
标题翻译：带有边缘时钟的偏光时钟分配网络
公开(公告)号：US5712579A
公开(公告)日：1998-01-27
申请号：US543693
申请日：1995-10-16
申请人： Khue Duong , Stephen M. Trimberger , Robert O. Conn, Jr. , John E. Mahoney
发明人： Khue Duong , Stephen M. Trimberger , Robert O. Conn, Jr. , John E. Mahoney
IPC分类号： H03K5/15 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/17704 , H03K5/1502
摘要： A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip. An edge clock is provided that is not deskewed and is directly coupled to an edge clock distribution system along the left and right edges of the IC to supply a clock signal to an entire edge or half of an edge with less delay relative to the deskewed clock. Also, a super fast edge clock is provided for very high speed circuits.
摘要翻译：一种用于集成电路（IC）的时钟分配网络及其机构，包括用于其的边缘时钟和分配系统。本发明包括用于位于列中的电路的偏斜校正时钟分配网络，其中缓冲在小于IC长度的一半的列中进行。该机构允许至少八个垂直列分配线中的每一个与至少八行的任何水平时钟供应线耦合。水平时钟电源线包括局部互连输入。为了增加时钟源信号，提供专门的线路Kx线，它们在+ E中进行缓冲和定向移动，从上到下，从上到下和上下中间的1/4 + EE IC长度。 Kx线可以来自进位信号，IOB，互连或从边沿时钟提供到时钟线，延长线或互连线。 Kx线允许垂直信号位移，例如芯片内的时钟信号等。提供边缘时钟，其不进行去校正，并且沿着IC的左边缘和右边缘直接耦合到边缘时钟分配系统，以将时钟信号提供给相对于偏移校正时钟的延迟较小的边缘的整个边缘或一半。此外，为超高速电路提供超快速时钟。

7. 发明授权

US4855669A System for scan testing of logic circuit networks 失效
标题翻译：逻辑电路网络扫描测试系统
公开(公告)号：US4855669A
公开(公告)日：1989-08-08
申请号：US106750
申请日：1987-10-07
申请人： John E. Mahoney
发明人： John E. Mahoney
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
CPC分类号： G01R31/318541
摘要： The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.
摘要翻译：通过使用包括通过晶体管的开关装置来验证电路处理逻辑信号的完整性，所述开关装置被选择性地变化以便为不同的操作模式提供不同的测试电路配置。电路工作在正常，扫描，测试和数据接收模式。在正常工作期间，来自主电路的逻辑信号直接通过逻辑测试块，而不会在逻辑测试块中移动数据。

8. 发明授权

US5234092A Control valve assembly with concentric spools 失效
标题翻译：带同心阀芯的控制阀总成
公开(公告)号：US5234092A
公开(公告)日：1993-08-10
申请号：US943098
申请日：1992-09-10
申请人： John E. Mahoney
发明人： John E. Mahoney
IPC分类号： F16D48/02 , F16H61/02 , F16H61/06
CPC分类号： F16H61/065 , F16D48/0206 , F16H61/0267 , F16D2048/0209 , F16D2048/0224 , F16D2500/70406
摘要： A control valve mechanism has concentric spool valve members that are selectively positionable to provide control pressure. The control pressure may be used for the selective actuation of fluid operated friction torque transmitting devices, such as clutches and brakes, in a power transmission.
摘要翻译：控制阀机构具有可选择性地定位以提供控制压力的同心滑阀构件。控制压力可用于在动力传动中选择性地致动流体操作的摩擦扭矩传递装置，例如离合器和制动器。

9. 发明授权

US4610177A Preselected multiratio transmission 失效
标题翻译：预选的多速率传输
公开(公告)号：US4610177A
公开(公告)日：1986-09-09
申请号：US705206
申请日：1985-02-25
申请人： John E. Mahoney
发明人： John E. Mahoney
IPC分类号： F16H3/00 , F16H3/089 , F16H3/093 , F16H3/08
CPC分类号： F16H3/089 , F16H2200/0047 , F16H3/006 , Y10T74/19228 , Y10T74/194
摘要： A preselected multiratio transmission has three selectively engageable input friction clutches and three selectively engageable synchronized mechanical ratio clutches. The friction clutches are connected with respective input shafts each of which shafts has two input ratio gears rotatably mounted thereon and one of the synchronized clutches connected therewith. Each synchronized clutch is operable to control two gear ratios. A countershaft has a plurality of output ratio gears connected therewith, which gears mesh with respective ones of the input ratio gears. The countershaft is drivingly connected with a transmission output means. The synchronized clutches are operated to preselect a drive ratio which is then completed by the engagement of the friction clutch associated therewith and the substantially simultaneous disengagement of either of the other friction clutches which may have been engaged. The judicious selection of friction clutches and synchronized clutches permits the transmission to be operated in a conventional step ratio pattern or in a plurality of skip ratio patterns.
摘要翻译：预选的多波轮变速器具有三个可选择性接合的输入摩擦离合器和三个可选择性接合的同步机械比离合器。摩擦离合器与相应的输入轴连接，每个轴具有可旋转地安装在其上的两个输入比齿轮和与之相连的同步离合器之一。每个同步离合器可操作以控制两个传动比。中间轴具有与其连接的多个输出比齿轮，齿轮与相应的输入比齿轮啮合。中间轴与变速器输出装置驱动连接。操作同步离合器以预先选择一个驱动比，该驱动比然后通过与其相关联的摩擦离合器的接合和可能已经接合的其它摩擦离合器的基本上同时的分离而完成。摩擦离合器和同步离合器的明智选择允许变速器以常规步进比例模式或多个跳动比例模式操作。

10. 发明授权

US5367207A Structure and method for programming antifuses in an integrated circuit array 失效
标题翻译：用于在集成电路阵列中编程反熔丝的结构和方法
公开(公告)号：US5367207A
公开(公告)日：1994-11-22
申请号：US625732
申请日：1990-12-04
申请人： F. Erich Goetting , David B. Parlour , John E. Mahoney
发明人： F. Erich Goetting , David B. Parlour , John E. Mahoney
IPC分类号： G01R31/317 , G11C17/18 , H01L21/82 , H03K19/177 , H03K3/01 , H03K5/08 , H03K19/092
CPC分类号： G11C17/18
摘要： This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied. The structure also allows for testing of logic devices by applying test voltages to the programming voltage lines and/or sensing logic device output on programming voltage lines. The structure and method also permit measuring resistance of the programmed antifuses. No separate testing overhead structure is needed.
摘要翻译：本发明提供了一种用于通过线段互连逻辑器件的结构和方法，其可以通过编程反熔丝来连接。几条编程线之一可以通过互连线段连接到阵列中每个反熔丝的每个端子。连接到相同反熔丝的相对端子的互连线段连接到不同的编程线，以便能够向反熔丝的两个端子施加不同的电压。寻址结构将互连线段选择性地连接到它们各自的编程线，并且施加到编程线的编程电压使得所选择的反熔丝被编程。一种新颖的寻址特征顺序地寻址要连接的线段的两个晶体管，并且利用电容性泵浦解码器来维持寻址晶体管在编程电压被施加时导通。该结构还允许通过对编程电压线上的编程电压线和/或感测逻辑器件输出施加测试电压来测试逻辑器件。该结构和方法还允许测量编程反熔丝的电阻。不需要单独的测试开销结构。

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