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1. 发明授权

US08397129B2 Memory array error correction apparatus, systems, and methods 有权
标题翻译：存储器阵列纠错装置，系统和方法
公开(公告)号：US08397129B2
公开(公告)日：2013-03-12
申请号：US13467699
申请日：2012-05-09
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器上接收要写入存储器阵列的多个数据突发的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

2. 发明申请

US20120221916A1 MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：存储器阵列错误校正装置，系统和方法
公开(公告)号：US20120221916A1
公开(公告)日：2012-08-30
申请号：US13467699
申请日：2012-05-09
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

3. 发明授权

US07945840B2 Memory array error correction apparatus, systems, and methods 有权
标题翻译：存储器阵列纠错装置，系统和方法
公开(公告)号：US07945840B2
公开(公告)日：2011-05-17
申请号：US11705190
申请日：2007-02-12
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

4. 发明授权

US08181086B2 Memory array error correction apparatus, systems, and methods 有权
标题翻译：存储器阵列纠错装置，系统和方法
公开(公告)号：US08181086B2
公开(公告)日：2012-05-15
申请号：US13086137
申请日：2011-04-13
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

5. 发明申请

US20110191655A1 MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：存储器阵列错误校正装置，系统和方法
公开(公告)号：US20110191655A1
公开(公告)日：2011-08-04
申请号：US13086137
申请日：2011-04-13
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

6. 发明申请

US20080195894A1 Memory array error correction apparatus, systems, and methods 有权
标题翻译：存储器阵列纠错装置，系统和方法
公开(公告)号：US20080195894A1
公开(公告)日：2008-08-14
申请号：US11705190
申请日：2007-02-12
申请人： John F. Schreck , Todd A. Dauenbaugh
发明人： John F. Schreck , Todd A. Dauenbaugh
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译：各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器的连续时钟周期。错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。

7. 发明授权

US06191995B1 Sharing signal lines in a memory device 有权
标题翻译：在存储设备中共享信号线
公开(公告)号：US06191995B1
公开(公告)日：2001-02-20
申请号：US09386101
申请日：1999-08-30
申请人： Brian W. Huber , Todd A. Dauenbaugh
发明人： Brian W. Huber , Todd A. Dauenbaugh
IPC分类号： G11C1300
CPC分类号： G11C5/025 , G11C5/063
摘要： A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.
摘要翻译：存储器件包括存储器阵列和至少两组行解码器以驱动存储器阵列中的行线。选择行（例如行选择行）携带信号以在两组解码器之一中选择一个或多个解码器。至少一些选择线在两组行解码器之间共享，以减少在存储器阵列中路由信号线所需的空间。

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